Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10795809 | Non-volatile logic device for energy-efficient logic state restoration | Jinghua Yang, Sarma Vrudhula | 2020-10-06 |
| 10551869 | Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designs | Sarma Vrudhula, Niranjan Kulkarni | 2020-02-04 |
| 9876503 | Method of obfuscating digital logic circuits using threshold voltage | Sarma Vrudhula, Niranjan Kulkarni, Joseph Davis | 2018-01-23 |
| 6593226 | Method for adding features to a design layout and process for designing a mask | Edward O. Travis, Sejal Chheda, Tat-Kwan Yu, Mark S. Roberton, Ruiqi Tian +2 more | 2003-07-15 |
| 6500723 | Method for forming a well under isolation and structure thereof | Michael G. Khazhinsky, James W. Miller | 2002-12-31 |
| 6396158 | Semiconductor device and a process for designing a mask | Edward O. Travis, Sejal Chheda, Tat-Kwan Yu, Mark S. Roberton, Ruiqi Tian | 2002-05-28 |