Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11599497 | High performance interconnect | Zuoguo Wu, Debendra Das Sharma, Mohiuddin M. Mazumder, Jong-Ru Guo, Anupriya Sriramulu +2 more | 2023-03-07 |
| 11569617 | Pinfield with ground vias adjacent to an auxiliary signal conductor for crosstalk mitigation | — | 2023-01-31 |
| 10999924 | Sideband conductor resonance mitigation | Steven K. Krooswyk, Marc Wells | 2021-05-04 |
| 10996825 | Smartbook system having a synergistic page, spine, edge extension and power design | Christian Karl, Charles Magnuson, Sergei Babokhov | 2021-05-04 |
| 10811823 | Pinfield with ground vias adjacent to an auxiliary signal conductor for crosstalk mitigation | — | 2020-10-20 |
| 10804631 | PCIe card edge connector for power delivery | Manisha M. Nilange, Thane M. Larson, Horthense Delphine Tamdem | 2020-10-13 |
| 10789201 | High performance interconnect | Zuoguo Wu, Debendra Das Sharma, Mohiuddin M. Mazumder, Jong-Ru Guo, Anupriya Sriramulu +2 more | 2020-09-29 |
| 10602607 | Sideband conductor resonance mitigation | Steven K. Krooswyk, Marc Wells | 2020-03-24 |
| 10038281 | Pinfield crosstalk mitigation | — | 2018-07-31 |
| 9974161 | Sideband conductor resonance mitigation | Steven K. Krooswyk, Marc Wells | 2018-05-15 |
| 9660364 | System interconnect for integrated circuits | Todd Hinck, Sanka Ganesan | 2017-05-23 |
| 9599661 | Testing device for validating stacked semiconductor devices | — | 2017-03-21 |
| 9560760 | Reduction of resonance in connectors | — | 2017-01-31 |
| 9559445 | Card edge connectors | — | 2017-01-31 |
| 7605671 | Component-less termination for electromagnetic couplers used in high speed/frequency differential signaling | Tao Liang, Bo Zhang, John Critchlow, Larry R. Tate | 2009-10-20 |
| 7501586 | Apparatus and method for improving printed circuit board signal layer transitions | Tao Liang | 2009-03-10 |
| 7342969 | Signaling with multiple clocks | Larry R. Tate | 2008-03-11 |