Issued Patents All Time
Showing 26–50 of 207 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8798127 | Apparatus and methods for adaptive receiver delay equalization | Weiqi Ding, Wei Li | 2014-08-05 |
| 8787352 | Heterogeneous transceiver architecture for wide range programmability of programmable logic devices | Bill Bereza, Chong H. Lee, Rakesh Patel, Wilson Wong | 2014-07-22 |
| 8750406 | Multi-level amplitude signaling receiver | Mingde Pan, Weiqi Ding, Peng Li, Masashi Shimanouchi | 2014-06-10 |
| 8744012 | On-chip eye viewer architecture for highspeed transceivers | Weiqi Ding, Mingde Pan, Peng Li | 2014-06-03 |
| 8743943 | High-speed data reception circuitry and methods | Wilson Wong, Rakesh Patel | 2014-06-03 |
| 8723572 | Apparatus and methods to correct differential skew and/or duty cycle distortion | Weiqi Ding | 2014-05-13 |
| 8705602 | Equalizer circuitry with selectable tap positions and coefficients | Weiqi Ding, Mengchi Liu, Mingde Pan, Thungoc M. Tran | 2014-04-22 |
| 8699648 | Apparatus and methods of receiver offset calibration | Allen Chan, Wilson Wong | 2014-04-15 |
| 8692595 | Transceiver circuitry with multiple phase-locked loops | David W. Mendel, Ramanand Venkata | 2014-04-08 |
| 8669828 | Decoupling capacitor control circuitry | Wilson Wong, Allen Chan | 2014-03-11 |
| 8653853 | Differential interfaces for power domain crossings | Tim Tri Hoang, Lawrence D. Smith | 2014-02-18 |
| 8649461 | Lane-to-lane skew reduction in multi-channel, high-speed, transceiver circuitry | — | 2014-02-11 |
| 8626474 | Simulation tool for high-speed communications links | Peng Li, Masashi Shimanouchi, Thungoc M. Tran | 2014-01-07 |
| 8619931 | Multi-purpose phase-locked loop for low cost transceiver | Tien Duc Pham, Tim Tri Hoang, Thungoc M. Tran, Vinh Ho, Leon Zheng | 2013-12-31 |
| 8571059 | Apparatus and methods for serial interfaces with shared datapaths | Arch Zaliznyak, Ramanand Venkata, Surinder Singh, Henry Y. Lui, Tim Tri Hoang +1 more | 2013-10-29 |
| 8570197 | Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits | Toan Thanh Nguyen, Thungoc M. Tran, Arch Zaliznyak, Shoujun Wang, Ramanand Venkata +1 more | 2013-10-29 |
| 8542042 | Phase-locked loop architecture and clock distribution system | Tien Duc Pham, Richard G. Cliff | 2013-09-24 |
| 8537886 | Reconfigurable equalization architecture for high-speed receivers | Xiaoyan Su, Sriram Narayan | 2013-09-17 |
| 8537954 | Method and apparatus for multi-mode clock data recovery | Rakesh Patel, Wilson Wong, Tim Tri Hoang | 2013-09-17 |
| 8504882 | Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations | Peng Li, Masashi Shimanouchi, Weiqi Ding, Siriram Narayan, Daniel Tun Lai Chow +1 more | 2013-08-06 |
| 8464088 | Multiple channel bonding in a high speed clock network | Toan Thanh Nguyen, Tim Tri Hoang, Weiqi Ding, Thungoc M. Tran | 2013-06-11 |
| 8451883 | On-chip full eye viewer architecture | Weiqi Ding, Mingde Pan, Peng Li | 2013-05-28 |
| 8433958 | Bit error rate checker receiving serial data signal from an eye viewer | Weiqi Ding, Mingde Pan, Peng Li, Masashi Shimanouchi | 2013-04-30 |
| 8417752 | Offset cancellation in equalizer circuitry | Doris Po Ching Chan, Simardeep Maangat, Thungoc M. Tran | 2013-04-09 |
| 8416845 | Decision feedback equalization for variable input amplitude | Wilson Wong, Rakesh Patel, Tim Tri Hoang | 2013-04-09 |