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Methods and apparatus for performing design for debug via protocol interface |
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2020-12-15 |
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Apparatus and methods for multiple-channel direct memory access |
Harry Nguyen, Michael Chen |
2017-06-20 |
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High-speed peripheral component interconnect (PCIe) input-output devices with receive buffer management circuitry |
Christopher D. Finan, Kenny Au, Cora Lynn Mau |
2017-01-24 |
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High-level language code sequence optimization for implementing programmable chip designs |
Jeffrey Orion Pritchard, Jarrod Colin James Blackburn, David James Lau, James Ball, Jesse Kempa |
2016-05-03 |
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Partial reconfiguration using configuration transaction layer packets |
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2016-02-09 |
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Modular direct memory access system |
Harry Nguyen, Christopher D. Finan |
2015-06-09 |
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DSP design system level power estimation |
Jordan Plofsky, Francois Pequillat |
2014-02-25 |
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High-level language code sequence optimization for implementing programmable chip designs |
Jeffrey Orion Pritchard, Jarrod Colin James Blackburn, David James Lau, James Ball, Jesse Kempa |
2013-11-05 |
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DSP design system level power estimation |
Jordan Plofsky, Francois Pequillat |
2013-03-19 |
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Scheduling optimization of aliased pointers for implementation on programmable chips |
David James Lau, Jeffrey Orion Pritchard |
2012-10-16 |
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Method and apparatus for providing protected intellectual property |
Tony San |
2012-06-12 |
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Embedded logic analyzer functionality for system level environments |
Maria D'Souza |
2011-08-02 |
| 7882457 |
DSP design system level power estimation |
Jordan Plofsky, Francois Pequillat |
2011-02-01 |
| 7873953 |
High-level language code sequence optimization for implementing programmable chip designs |
Jeffrey Orion Pritchard, Jarrod Colin James Blackburn, David James Lau, James Ball, Jesse Kempa |
2011-01-18 |
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Finite impulse response (FIR) filter compiler for estimating cost of implementing a filter |
Tony San |
2011-01-04 |
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Method and apparatus for providing protected intellectual property |
Tony San |
2010-03-09 |
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System level simulation models for hardware modules |
Tony San, Jeffrey R. Fox |
2009-03-24 |
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Finite impulse response (FIR) filter compiler |
Tony San |
2009-01-20 |
| 7360189 |
Method and apparatus for enabling waveform display in a system design model |
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2008-04-15 |
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Bit accurate hardware simulation in system level simulators |
Tony San |
2008-01-08 |
| 7181384 |
Method and apparatus for simulating a hybrid system with registered and concurrent nodes |
Adam Schott Riggs |
2007-02-20 |
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DSP design system level power estimation |
Jordan Plofsky, Francois Pequillat |
2006-11-28 |
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Finite impulse response (FIR) filter compiler |
Tony San |
2006-09-19 |
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Hardware opencore evaluation |
Tony San |
2006-08-08 |
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Interleaver-deinterleaver megacore |
Tony San |
2003-10-14 |