Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7725713 | Launching a secure kernel in a multiprocessor system | John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock +3 more | 2010-05-25 |
| 7721148 | Method and apparatus for redirection of machine check interrupts in multithreaded systems | Scott Brenden, Suresh Marisetty | 2010-05-18 |
| 7698552 | Launching a secure kernel in a multiprocessor system | John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock +3 more | 2010-04-13 |
| 7587639 | System and method for error injection using a flexible program interface field | Suresh Marisetty, Rajendra Kuramkote, Koichi Yamada, Scott Brenden | 2009-09-08 |
| 7426648 | Global and pseudo power state management for multiple processing elements | Bernard Lint, Todd Dutton | 2008-09-16 |
| 7360103 | P-state feedback to operating system with hardware coordination | Bernard Lint, Alon Naveh, Shivnandan Kaushik, Jeffrey R. Wilcox, Lance Hacking +2 more | 2008-04-15 |
| 7353433 | Poisoned error signaling for proactive OS recovery | Suresh Marisetty, Yaron Shragai, Koichi Yamada, Rajendra Kuramkote, Scott Brenden | 2008-04-01 |
| 7254676 | Processor cache memory as RAM for execution of boot code | Sham M. Datta, Vincent J. Zimmer, William A. Stevens, Amy L. Santoni | 2007-08-07 |
| 7213129 | Method and system for a two stage pipelined instruction decode and alignment using previous instruction length | Fred Gruner, Mike Morrison | 2007-05-01 |
| 6684322 | Method and system for instruction length decode | Fred Gruner, Mike Morrison | 2004-01-27 |
| 6598154 | Precoding branch instructions to reduce branch-penalty in pipelined processors | Frederick Gruner | 2003-07-22 |
| 6112295 | High frequency pipeline decoupling queue with non-overlapping read and write signals within a single clock cycle | Sriram Bhamidipati | 2000-08-29 |