Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10963986 | Adaptive compute size per workload | Balaji Vembu, Altug Koker, Nikos Kaburlasos, Abhishek R. Appu, Joydeep Ray | 2021-03-30 |
| 10929947 | Contextual configuration adjuster for graphics | Joydeep Ray, Ankur N. Shah, Abhishek R. Appu, Deepak S. Vembar, Elmoustapha Ould-Ahmed-Vall +4 more | 2021-02-23 |
| 10909652 | Enabling product SKUs based on chiplet configurations | Altug Koker, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar +6 more | 2021-02-02 |
| 10902547 | Compute optimization mechanism for deep neural networks | Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh +22 more | 2021-01-26 |
| 10891773 | Apparatus and method for efficient graphics virtualization | Joydeep Ray, Abhishek R. Appu, Pattabhiraman K, Balaji Vembu, Altug Koker +1 more | 2021-01-12 |
| 10803548 | Disaggregation of SOC architecture | Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar +6 more | 2020-10-13 |
| 10565671 | Reduce power by frame skipping | Balaji Vembu, Nikos Kaburlasos | 2020-02-18 |
| 10528118 | Dynamically power on/off register files during execution | Balaji Vembu, Nikos Kaburlasos | 2020-01-07 |
| 10521271 | Hybrid low power homogenous grapics processing units | Abhishek R. Appu, Altug Koker, Balaji Vembu, Joydeep Ray, Kamal Sinha +16 more | 2019-12-31 |
| 10521880 | Adaptive compute size per workload | Balaji Vembu, Altug Koker, Nikos Kaburlasos, Abhishek R. Appu, Joydeep Ray | 2019-12-31 |
| 10503520 | Automatic waking of power domains for graphics configuration requests | William S. Dubel, Melaku Teshome | 2019-12-10 |
| 10460415 | Contextual configuration adjuster for graphics | Joydeep Ray, Ankur N. Shah, Abhishek R. Appu, Deepak S. Vembar, Elmoustapha Ould-Ahmed-Vall +4 more | 2019-10-29 |
| 10430310 | Dynamic voltage-frequency curve management | Nikos Kaburlasos, Balaji Vembu, Altug Koker, Eric C. Samson, Abhishek R. Appu +4 more | 2019-10-01 |
| 10417731 | Compute optimization mechanism for deep neural networks | Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh +22 more | 2019-09-17 |
| 10417734 | Compute optimization mechanism for deep neural networks | Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh +22 more | 2019-09-17 |
| 9250910 | Current change mitigation policy for limiting voltage droop in graphics logic | Linda L. Hurd, Wenyin Fu, Pradeep K. Golconda, Shalini Sankar, Eric C. Samson | 2016-02-02 |
| 7051172 | Memory arbiter with intelligent page gathering logic | Aditya Sreenivas, Thomas A. Piazza | 2006-05-23 |
| 7035984 | Memory arbiter with grace and ceiling periods and intelligent page gathering logic | Aditya Sreenivas, Thomas A. Piazza | 2006-04-25 |
| 6792516 | Memory arbiter with intelligent page gathering logic | Aditya Sreenivas, Thomas A. Piazza | 2004-09-14 |
| 6593931 | Method and apparatus for improving system memory bandwidth utilization during graphics translational lookaside buffer cache miss fetch cycles | Russell W. Dyer, Himanshu Sinha | 2003-07-15 |
| 6510472 | Dual input lane reordering data buffer | — | 2003-01-21 |