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USPTO Patent Rankings Data through Sept 30, 2025
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Ioannis T. Schoinas — 65 Patents

Intel: 65 patents #432 of 30,777Top 2%
Portland, OR: #242 of 9,213 inventorsTop 3%
Oregon: #458 of 28,073 inventorsTop 2%
Overall (All Time): #33,340 of 4,157,543Top 1%
65 Patents All Time

Issued Patents All Time

Showing 51–65 of 65 patents

Patent #TitleCo-InventorsDate
7725713 Launching a secure kernel in a multiprocessor system John H. Wilson, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert Greiner +3 more 2010-05-25
7698552 Launching a secure kernel in a multiprocessor system John H. Wilson, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert Greiner +3 more 2010-04-13
7467381 Resource partitioning and direct access utilizing hardware support for virtualization Rajesh Madukkarumukumana, Gilbert Neiger 2008-12-16
7444493 Address translation for input/output devices using hierarchical translation tables Rajesh Madukkarumakumana, Gilbert Neiger, Richard Uhlig, Ku-Jei King 2008-10-28
7433985 Conditional and vectored system management interrupts Mani Ayyar, Rama Menon, Aniruddha Vaidya, Akhilesh Kumar 2008-10-07
7340582 Fault processing for direct memory access address translation Rajesh Madukkarumukumana, Ku-Jei King, Balaji Vembu, Gilbert Neiger, Richard Uhlig 2008-03-04
7334107 Caching support for direct memory access address translation Rajesh Madukkarumukumana, Gilbert Neiger, Richard Uhlig, Balaji Vembu 2008-02-19
7328368 Dynamic interconnect width reduction to improve interconnect availability Phanindra Kumar Mannava, Victor W. Lee, Akhilesh Kumar, Doddaballapur N. Jayasimha 2008-02-05
7257682 Synchronizing memory copy operations with memory accesses Siva Ramakrishnan 2007-08-14
7222203 Interrupt redirection for virtual partitioning Rajesh Madukkarumukumana, Gilbert Neiger 2007-05-22
7127566 Synchronizing memory copy operations with memory accesses Siva Ramakrishnan 2006-10-24
7127567 Performing memory RAS operations over a point-to-point interconnect Siva Ramakrishnan 2006-10-24
6971098 Method and apparatus for managing transaction requests in a multi-node architecture Manoj Khare, Akhilesh Kumar, Lily P. Looi 2005-11-29
6662276 Storing directory information for non uniform memory architecture systems using processor cache 2003-12-09
6347362 Flexible event monitoring counters in multi-node processor systems and process of operating the same Ali S. Oztaskin 2002-02-12