Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6931505 | Distributed memory module cache command formatting | — | 2005-08-16 |
| 6925534 | Distributed memory module cache prefetch | — | 2005-08-02 |
| 6880044 | Distributed memory module cache tag look-up | — | 2005-04-12 |
| 6865646 | Segmented distributed memory module cache | — | 2005-03-08 |
| 6832177 | Method of addressing individual memory devices on a memory module | Narendra S. Khandekar | 2004-12-14 |
| 6795899 | Memory system with burst length shorter than prefetch length | James M. Dodd | 2004-09-21 |
| 6026460 | Method and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge to improve bus efficiency | Michael J. McTague | 2000-02-15 |
| 5668949 | System utilizing multiple address decode resources and decoder receiving address determines address corresponding to resource based on select and ready signals by that particular resource | Joseph M. Nardone, Michael J. McTague | 1997-09-16 |
| 5590289 | Method and apparatus for initializing a computer system having central and distributed address decode memory bus resources | Joseph M. Nardone, Michael J. McTague | 1996-12-31 |
| 5537640 | Asynchronous modular bus architecture with cache consistency | Stephen S. Pawlowski, Peter D. MacWilliams, David Cowan | 1996-07-16 |
| 5437021 | Programmable dedicated timer operating on a clock independent of processor timer | Orville H. Christeson | 1995-07-25 |