Issued Patents All Time
Showing 26–50 of 161 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8443169 | Interconnection network connecting operation-configurable nodes according to one or more levels of adjacency in multiple dimensions of communication in a multi-processor and a neural processor | — | 2013-05-14 |
| 8413086 | Methods and apparatus for adapting pipeline stage latency based on instruction type | Edwin Franklin Barry, Patrick R. Marchand | 2013-04-02 |
| 8397000 | System core for transferring data between an external device and memory | David Strube, Edwin Franklin Barry, Charles W. Kurak, Jr., Carl Donald Busboom, Dale Edward Schneider +6 more | 2013-03-12 |
| 8385419 | Methods and apparatus for motion search refinement in a SIMD array processor | Mihailo M. Stojancic | 2013-02-26 |
| 8358695 | Methods and apparatus for providing a scalable motion estimation/compensation assist function within an array processor | Mihailo M. Stojancic | 2013-01-22 |
| 8341381 | Twisted and wrapped array organized into clusters of processing elements | Charles W. Kurak, Jr. | 2012-12-25 |
| 8335812 | Methods and apparatus for efficient complex long multiplication and covariance matrix implementation | Ricardo E. Rodriguez, Matthew Plonski, David Strube, Kevin Coopman | 2012-12-18 |
| 8296479 | System core for transferring data between an external device and memory | David Strube, Edwin Franklin Barry, Charles W. Kurak, Jr., Carl Donald Busboom, Dale Edward Schneider +6 more | 2012-10-23 |
| 8266410 | Meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors | — | 2012-09-11 |
| 8255664 | Methods and apparatus for address translation functions | Edwin Franklin Barry | 2012-08-28 |
| 8208553 | Methods and apparatus for quarter-pel refinement in a SIMD array processor | Mihailo M. Stojancic | 2012-06-26 |
| 8195732 | Methods and apparatus for single stage Galois field operations | Nikos P. Pitsianis | 2012-06-05 |
| 8161267 | Methods and apparatus for scalable array processor interrupt detection and response | Edwin Franklin Barry, Patrick R. Marchand, Larry D. Larsen | 2012-04-17 |
| 8156311 | Interconnection networks and methods of construction thereof for efficiently sharing memory and processing in a multiprocessor wherein connections are made according to adjacency of nodes in a dimension | — | 2012-04-10 |
| 8117357 | System core for transferring data between an external device and memory | David Strube, Edwin Frank Barry, Charles W. Kurak, Jr., Carl Donald Busboom, Dale Edward Schneider +6 more | 2012-02-14 |
| 8103854 | Methods and apparatus for independent processor node operations in a SIMD array processor | Edwin Franklin Barry, Mihailo M. Stojancic | 2012-01-24 |
| 8069337 | Methods and apparatus for dynamic instruction controlled reconfigurable register file | Edward A. Wolff | 2011-11-29 |
| 7971036 | Methods and apparatus for attaching application specific functions within an array processor | Mihailo M. Stojancic | 2011-06-28 |
| 7962723 | Methods and apparatus storing expanded width instructions in a VLIW memory deferred execution | Stamatis Vassiliadis | 2011-06-14 |
| 7962719 | Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture | Nikos P. Pitsianis, Ricardo E. Rodriguez | 2011-06-14 |
| 7962667 | System core for transferring data between an external device and memory | David Strube, Edwin Frank Barry, Charles W. Kurak, Jr., Carl Donald Busboom, Dale Edward Schneider +6 more | 2011-06-14 |
| 7953955 | Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture | Sergei Larin, Thomas Martin Conte | 2011-05-31 |
| 7945760 | Methods and apparatus for address translation functions | Edwin Franklin Barry | 2011-05-17 |
| 7941648 | Methods and apparatus for dynamic instruction controlled reconfigurable register file | Edward A. Wolff | 2011-05-10 |
| 7886128 | Interconnection network and method of construction thereof for efficiently sharing memory and processing in a multi-processor wherein connections are made according to adjacency of nodes in a dimension | — | 2011-02-08 |