Issued Patents All Time
Showing 26–50 of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6879183 | Programmable logic device architectures with super-regions having logic regions and a memory region | Cameron McClintock, James Schleicher, Andy L. Lee, Manuel Mejia, Bruce B. Pedersen +3 more | 2005-04-12 |
| 6826741 | Flexible I/O routing resources | Brian Johnson, Andy L. Lee, Cameron McClintock, Triet Nguyen, Paul Leventis +3 more | 2004-11-30 |
| 6815981 | Programmable logic array integrated circuit devices | Richard G. Cliff, Srinivas T. Reddy, Rina Raman, L. Todd Cope, Christopher F. Lane +7 more | 2004-11-09 |
| 6798242 | Programmable logic device with hierarchical interconnection resources | Srinivas T. Reddy, Richard G. Cliff, Christopher F. Lane, Ketan Zaveri, Manuel Mejia +2 more | 2004-09-28 |
| 6759871 | Line segmentation in programmable logic devices having redundancy circuitry | Triet Nguyen, Changsong Zhang | 2004-07-06 |
| 6720796 | Multiple size memories in a programmable logic device | Srinivas T. Reddy, Christopher F. Lane, Vikram Santurkar, Richard G. Cliff | 2004-04-13 |
| 6657456 | Programmable logic with on-chip DLL or PLL to distribute clock | L. Todd Cope, Srinivas T. Reddy, Richard G. Cliff | 2003-12-02 |
| 6600337 | Line segmentation in programmable logic devices having redundancy circuitry | Triet Nguyen, Changsong Zhang | 2003-07-29 |
| 6577160 | Programmable logic device with hierarchical interconnection resources | Srinivas T. Reddy, Richard G. Cliff, Christopher F. Lane, Ketan Zaveri, Manuel Mejia +2 more | 2003-06-10 |
| 6480028 | Programmable logic device architectures with super-regions having logic regions and memory region | Cameron McClintock, James Schleicher, Andy L. Lee, Manuel Mejia, Bruce Pederson +3 more | 2002-11-12 |
| 6459303 | High speed programmable address decoder | Wanli Chang | 2002-10-01 |
| 6417694 | Programmable logic device with hierarchical interconnection resources | Srinivas T. Reddy, Richard G. Cliff, Christopher F. Lane, Ketan Zaveri, Manuel Mejia +2 more | 2002-07-09 |
| 6392438 | Programmable logic array integrated circuit devices | Richard G. Cliff, Srinivas T. Reddy, Rina Raman, L. Todd Cope, Christopher F. Lane +7 more | 2002-05-21 |
| 6337578 | Redundancy circuitry for programmable logic devices with interleaved input circuits | Srinivas T. Reddy | 2002-01-08 |
| 6326812 | Programmable logic device with logic signal delay compensated clock network | — | 2001-12-04 |
| 6300794 | Programmable logic device with hierarchical interconnection resources | Srinivas T. Reddy, Richard G. Cliff, Christopher F. Lane, Ketan Zaveri, Manuel Mejia +2 more | 2001-10-09 |
| 6292016 | Programmable logic with on-chip DLL or PLL to distribute clock | L. Todd Cope, Srinivas T. Reddy, Richard G. Cliff | 2001-09-18 |
| 6278288 | Programmable logic device with enhanced multiplexing capabilities in interconnect resources | Andy L. Lee, Richard G. Cliff, Cameron McClintock, Kurosu R. Altaf | 2001-08-21 |
| 6262933 | High speed programmable address decoder | Wanli Chang | 2001-07-17 |
| 6225823 | Input/output circuitry for programmable logic devices | Christopher F. Lane, Srinivas T. Reddy, Andy L. Lee | 2001-05-01 |
| 6222382 | Redundancy circuitry for programmable logic devices with interleaved input circuits | Srinivas T. Reddy | 2001-04-24 |
| 6215326 | Programmable logic device architecture with super-regions having logic regions and a memory region | Cameron McClintock, James Schleicher, Andy L. Lee, Manuel Mejia, Bruce B. Pedersen +3 more | 2001-04-10 |
| 6163195 | Temperature compensated delay chain | — | 2000-12-19 |
| 6130552 | Programmable logic integrated circuit with on-chip DLL or PLL for clock distribution | L. Todd Cope, Srinivas T. Reddy, Richard G. Cliff | 2000-10-10 |
| 6127865 | Programmable logic device with logic signal delay compensated clock network | — | 2000-10-03 |