Issued Patents All Time
Showing 26–50 of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10921872 | Performing soft throttling and hard throttling in a processor | Elkana Korem, Hanan Shomroni, Nadav Shulman | 2021-02-16 |
| 10809790 | Dynamic voltage-level clock tuning | Yiftach Gilad, Ariel Szapiro, Elkana Korem | 2020-10-20 |
| 10775434 | System, apparatus and method for probeless field scan of a processor | Michael Mishaeli, Larisa Novakovsky, Edward Brazil | 2020-09-15 |
| 10719326 | Communicating via a mailbox interface of a processor | Larisa Novakovsky, Ariel Szapiro | 2020-07-21 |
| 10705559 | Current sensor based closed loop control apparatus | Kosta Luria, Arye Albahari, Ohad Nachshon | 2020-07-07 |
| 10663998 | Autonomous phase shedding control for a voltage regulator | Tamir Salus, Alexander Lyakhov, Krishnakanth V. Sistla, Ankush Varma, Rachid E. Rayess +1 more | 2020-05-26 |
| 10628542 | Core-only system management interrupt | Tsvika Kurts, Larisa Novakovsky, Anwar Azaarura Zaa'Rura, Afik Sela, Genadi Kazakevich +2 more | 2020-04-21 |
| 10613611 | Current control for a multicore processor | Efraim Rotem, Nir Rosenzweig, Krishnakanth V. Sistla, Ashish V. Choubal, Ankush Varma | 2020-04-07 |
| 10503509 | System and method for communication using a register management array circuit | Eliezer Weissmann, Michael Mishaeli | 2019-12-10 |
| 10437315 | System, apparatus and method for dynamically controlling error protection features of a processor | Arkady Bramnik, Lev Makovsky | 2019-10-08 |
| 10365707 | Instruction and logic for parallel multi-step power management flow | Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell | 2019-07-30 |
| 10345889 | Forcing a processor into a low power state | Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem +11 more | 2019-07-09 |
| 10289188 | Processor having concurrent core and fabric exit from a low power state | Henrietta Bezbroz | 2019-05-14 |
| 10268255 | Management of system current constraints with current limits for individual engines | Nir Rosenzweig, Efraim Rotem, Ankush Varma | 2019-04-23 |
| 10198027 | Providing reduced latency credit information in a processor | Ariel Szapiro, Mark Gutman | 2019-02-05 |
| 10126775 | Current sensor based closed loop control apparatus | Kosta Luria, Arye Albahari, Ohad Nachshon | 2018-11-13 |
| 10114435 | Method and apparatus to control current transients in a processor | — | 2018-10-30 |
| 9933845 | Apparatus and method to provide multiple domain clock frequencies in a processor | — | 2018-04-03 |
| 9910470 | Controlling telemetry data communication in a processor | Vivek Garg, Arvind Raman, Ashish V. Choubal, Krishnakanth V. Sistla, Dean Mulla +3 more | 2018-03-06 |
| 9891695 | Flushing and restoring core memory content to external memory | Ariel Berkovits, Michael Mishaeli, Nadav Shulman, Sameer Desai, Shani Rehana +2 more | 2018-02-13 |
| 9772678 | Utilization of processor capacity at low operating frequencies | Ruchira Sasanka, Udi Sherel | 2017-09-26 |
| 9760158 | Forcing a processor into a low power state | Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem +11 more | 2017-09-12 |
| 9748977 | Double consecutive error correction | Gilad Cohen | 2017-08-29 |
| 9710041 | Masking a power state of a core of a processor | Larisa Novakovsky, Krishnakanth V. Sistla, Vivek Garg, Dean Mulla, Ashish V. Choubal +2 more | 2017-07-18 |
| 9684595 | Adaptive hierarchical cache policy in a microprocessor | Larisa Novakovsky, Joseph Nuzman | 2017-06-20 |