| 5649232 |
Structure and method for multiple-level read buffer supporting optimal throttled read operations by regulating transfer rate |
Philip A. Bourekas, Avigdor Willenz, Yeshayahu Mor |
1997-07-15 |
| 5636363 |
Hardware control structure and method for off-chip monitoring entries of an on-chip cache |
Philip A. Bourekas, Yeshayahu Mor |
1997-06-03 |
| 5517659 |
Multiplexed status and diagnostic pins in a microprocessor with on-chip caches |
Philip A. Bourekas, Yeshayahu Mor, Avigdor Willenz |
1996-05-14 |
| 5386579 |
Minimum pin-count multiplexed address/data bus with byte enable and burst address counter support microprocessor transmitting byte enable signals on multiplexed address/data bus having burst address counter for supporting signal datum and burst transfer |
Philip A. Bourekas, Avigdor Willenz, Yeshayahu Mor, Danh LeNgoc |
1995-01-31 |
| 5343435 |
Use of a data register to effectively increase the efficiency of an on-chip write buffer |
Philip A. Bourekas, Danh Le Ngoc |
1994-08-30 |
| 5317711 |
Structure and method for monitoring an internal cache |
Philip A. Bourekas, Yeshayahu Mor |
1994-05-31 |
| 5260902 |
Efficient redundancy method for RAM circuit |
David J. Pilling, Michael A. Ang |
1993-11-09 |