Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| RE44151 | Switching ethernet controller | David Shemla | 2013-04-16 |
| RE43058 | Switching ethernet controller | David Shemla | 2012-01-03 |
| RE41464 | Switching ethernet controller providing packet routing | David Shemla, Yosi Sholt | 2010-07-27 |
| RE39514 | Switching ethernet controller | David Shemla | 2007-03-13 |
| RE38821 | Switching ethernet controller | David Shemla | 2005-10-11 |
| 5999981 | Switching ethernet controller providing packet routing | David Shemla, Yosi Sholt | 1999-12-07 |
| 5923660 | Switching ethernet controller | David Shemla | 1999-07-13 |
| 5894176 | Flexible reset scheme supporting normal system operation, test and emulation modes | Philip A. Bourekas, Yeshayahu Mor | 1999-04-13 |
| 5841722 | First-in, first-out (FIFO) buffer | — | 1998-11-24 |
| 5809557 | Memory array comprised of multiple FIFO devices | David Shemla, Gerardo Waisbaum | 1998-09-15 |
| 5649232 | Structure and method for multiple-level read buffer supporting optimal throttled read operations by regulating transfer rate | Philip A. Bourekas, Yeshayahu Mor, Scott Revak | 1997-07-15 |
| 5590310 | Method and structure for data integrity in a multiple level cache system | Yiftach Tzori | 1996-12-31 |
| 5586303 | Structure and method for providing a cache memory of selectable sizes | Steven Eliscu, Martin Mueller | 1996-12-17 |
| 5553268 | Memory operations priority scheme for microprocessors | Philip A. Bourekas, Yehayahu Mor | 1996-09-03 |
| 5517659 | Multiplexed status and diagnostic pins in a microprocessor with on-chip caches | Philip A. Bourekas, Yeshayahu Mor, Scott Revak | 1996-05-14 |
| 5398211 | Structure and method for providing prioritized arbitration in a dual port memory | Kelly A. Maas | 1995-03-14 |
| 5386579 | Minimum pin-count multiplexed address/data bus with byte enable and burst address counter support microprocessor transmitting byte enable signals on multiplexed address/data bus having burst address counter for supporting signal datum and burst transfer | Philip A. Bourekas, Yeshayahu Mor, Danh LeNgoc, Scott Revak | 1995-01-31 |
| 5175859 | Apparatus for disabling unused cache tag input/output pins during processor reset by sensing pull-down resistors connected to disabled pins | Michael J. Miller, Philip A. Bourekas | 1992-12-29 |