Issued Patents All Time
Showing 26–50 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6839256 | Content addressable memory (CAM) devices having dedicated mask cell sub-arrays therein and methods of operating same | Kee Park, Scott Yu-Fan Chu | 2005-01-04 |
| 6804134 | Content addressable memory (CAM) devices having CAM array blocks therein that conserve bit line power during staged compare operations | Scott Yu-Fan Chu, Kee Park | 2004-10-12 |
| 6798629 | Overvoltage protection circuits that utilize capacitively bootstrapped variable voltages | — | 2004-09-28 |
| 6763406 | Noise reduction system and method for reducing switching noise in an interface to a large width bus | William L. Devanney | 2004-07-13 |
| 6549042 | Complementary data line driver circuits with conditional charge recycling capability that may be used in random access and content addressable memory devices and method of operating same | — | 2003-04-15 |
| 6462584 | GENERATING A TAIL CURRENT FOR A DIFFERENTIAL TRANSISTOR PAIR USING A CAPACITIVE DEVICE TO PROJECT A CURRENT FLOWING THROUGH A CURRENT SOURCE DEVICE ONTO A NODE HAVING A DIFFERENT VOLTAGE THAN THE CURRENT SOURCE DEVICE | — | 2002-10-08 |
| 6462998 | Programmable and electrically configurable latch timing circuit | — | 2002-10-08 |
| 6373753 | Memory array having selected word lines driven to an internally-generated boosted voltage that is substantially independent of VDD | — | 2002-04-16 |
| 6356485 | Merging write cycles by comparing at least a portion of the respective write cycle addresses | — | 2002-03-12 |
| 6326839 | Apparatus for translating a voltage | — | 2001-12-04 |
| 6323721 | Substrate voltage detector | — | 2001-11-27 |
| 6323722 | Apparatus for translating a voltage | — | 2001-11-27 |
| 6307417 | Integrated circuit output buffers having reduced power consumption requirements and methods of operating same | — | 2001-10-23 |
| 6282135 | Intializing memory cells within a dynamic memory array prior to performing internal memory operations | — | 2001-08-28 |
| 6266264 | Word line straps using two different layers of metal | — | 2001-07-24 |
| 6243779 | Noise reduction system and method for reducing switching noise in an interface to a large width bus | William L. Devanney | 2001-06-05 |
| 6240046 | Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle | — | 2001-05-29 |
| 6216205 | Methods of controlling memory buffers having tri-port cache arrays therein | Bruce Lorenz Chin | 2001-04-10 |
| 6212109 | Dynamic memory array having write data applied to selected bit line sense amplifiers before sensing to write associated selected memory cells | — | 2001-04-03 |
| 6208575 | Dynamic memory array bit line sense amplifier enabled to drive toward, but stopped before substantially reaching, a source of voltage | — | 2001-03-27 |
| 6198682 | Hierarchical dynamic memory array architecture using read amplifiers separate from bit line sense amplifiers | — | 2001-03-06 |
| 6163475 | Bit line cross-over layout arrangement | — | 2000-12-19 |
| 6154064 | Differential sense amplifier circuit | — | 2000-11-28 |
| 6137157 | Semiconductor memory array having shared column redundancy programming | — | 2000-10-24 |
| 6137335 | Oscillator receiving variable supply voltage depending on substrate voltage detection | — | 2000-10-24 |