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USPTO Patent Rankings Data through Dec 31, 2025
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William L. Devanney — 8 Patents

ITIntegrated Device Technology: 5 patents #128 of 758Top 20%
CLClearlogic: 3 patents #3 of 9Top 35%
Pacific Grove, CA: #21 of 128 inventorsTop 20%
California: #74,834 of 386,348 inventorsTop 20%
Overall (All Time): #600,572 of 4,157,543Top 15%
8 Patents All Time
William L. Devanney has been granted 8 US patents while listed as an inventor at Integrated Device Technology. The first was granted in 1995 and the most recent in July 2004. William L. Devanney ranks #600,572 of 4,157,543 US inventors in our database (top 14.4%). Patent records list William L. Devanney in Pacific Grove, CA, US.

Issued Patents All Time

Showing 1–8 of 8 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
6763406 Noise reduction system and method for reducing switching noise in an interface to a large width bus Robert J. Proebsting 2004-07-13 $14,421,000
6311316 Designing integrated circuit gate arrays using programmable logic device bitstreams Alan H. Huggins, David E. Schmulian, John MacPherson 2001-10-30
6243779 Noise reduction system and method for reducing switching noise in an interface to a large width bus Robert J. Proebsting 2001-06-05 $32,716,000
6225652 Vertical laser fuse structure allowing increased packing density 2001-05-01
6191641 Zero power fuse circuit using subthreshold conduction 2001-02-20
5910922 Method for testing data retention in a static random access memory using isolated V.sub.cc supply Alan H. Huggins, Chuen-Der Lien 1999-06-08 $7,563,000
5541883 Method and apparatus for simultaneous long writes of multiple cells of a row in a static ram 1996-07-30 $5,487,000
5440524 Method and apparatus for simuilataneous long writes of multiple cells of a row in a static ram 1995-08-08 $26,864,000