Issued Patents All Time
Showing 51–75 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6134176 | Disabling a defective element in an integrated circuit device having redundant elements | — | 2000-10-17 |
| 6115302 | Disabling a decoder for a defective element in an integrated circuit device having redundant elements | — | 2000-09-05 |
| 6104653 | Equilibration circuit and method using a pulsed equilibrate signal and a level equilibrate signal | — | 2000-08-15 |
| 6064250 | Various embodiments for a low power adaptive charge pump circuit | — | 2000-05-16 |
| 6044023 | Method and apparatus for pipelining data in an integrated circuit | — | 2000-03-28 |
| 6031783 | High speed video frame buffer | — | 2000-02-29 |
| 6026044 | High speed video frame buffer | — | 2000-02-15 |
| 5999478 | Highly integrated tri-port memory buffers having fast fall-through capability and methods of operating same | — | 1999-12-07 |
| 5995437 | Semiconductor memory and method of accessing memory arrays | — | 1999-11-30 |
| 5982700 | Buffer memory arrays having nonlinear columns for providing parallel data access capability and methods of operating same | — | 1999-11-09 |
| 5978307 | Integrated circuit memory devices having partitioned multi-port memory arrays therein for increasing data bandwidth and methods of operating same | Roland T. Knaack | 1999-11-02 |
| 5952948 | Low power liquid-crystal display driver | — | 1999-09-14 |
| 5939919 | Clock signal distribution method for reducing active power dissipation | — | 1999-08-17 |
| 5936905 | Self adjusting delay circuit and method for compensating sense amplifier clock timing | — | 1999-08-10 |
| 5926050 | Separate set/reset paths for time critical signals | — | 1999-07-20 |
| 5859961 | Renumbered array architecture for multi-array memories | — | 1999-01-12 |
| 5793383 | Shared bootstrap circuit | — | 1998-08-11 |
| 5740116 | Current limiting during block writes of memory circuits | — | 1998-04-14 |
| 5737267 | Word line driver circuit | — | 1998-04-07 |
| 5731713 | TTL to CMOS level translator with voltage and threshold compensation | Hyunsoo Sim | 1998-03-24 |
| 5713005 | Method and apparatus for pipelining data in an integrated circuit | — | 1998-01-27 |
| 5689462 | Parallel output buffers in memory circuits | — | 1997-11-18 |
| 5687108 | Power bussing layout for memory circuits | — | 1997-11-11 |
| 5585747 | High speed low power sense amplifier | — | 1996-12-17 |
| 5572471 | Redundancy scheme for memory circuits | — | 1996-11-05 |