Issued Patents All Time
Showing 76–100 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5546338 | Fast voltage equilibration of differential data lines | — | 1996-08-13 |
| 5546569 | Apparatus for writing data to and reading data from a multi-port RAM in a single clock cycle | Raymond A. Heald | 1996-08-13 |
| 5519344 | Fast propagation technique in CMOS integrated circuits | — | 1996-05-21 |
| 5499445 | Method of making a multi-layer to package | Steven R. Boyle, William H. Herndon | 1996-03-19 |
| 5495445 | Redundancy scheme for memory circuits | — | 1996-02-27 |
| 5479646 | Method and apparatus for obtaining data from a data circuit utilizing alternating clock pulses to gate the data to the output | — | 1995-12-26 |
| 5453951 | Fast voltage equilibration of complementary data lines following write cycle in memory circuits | — | 1995-09-26 |
| 5343090 | Speed enhancement technique for CMOS circuits | — | 1994-08-30 |
| 5338970 | Multi-layered integrated circuit package with improved high frequency performance | Steven R. Boyle, William H. Herndon | 1994-08-16 |
| 5305274 | Method and apparatus for refreshing a dynamic random access memory | — | 1994-04-19 |
| 5274593 | High speed redundant rows and columns for semiconductor memories | — | 1993-12-28 |
| 5216297 | Low voltage swing output MOS circuit for driving an ECL circuit | — | 1993-06-01 |
| 5212454 | Method and apparatus for selecting and measuring a capacitance from a plurality of interconnected capacitances | — | 1993-05-18 |
| 5057718 | CMOS regenerative sense amplifier with high speed latching | — | 1991-10-15 |
| 4985643 | Speed enhancement technique for CMOS circuits | — | 1991-01-15 |
| 4868421 | Bimos circuit that provides low power dissipation and high transient drive capability | William H. Herndon | 1989-09-19 |
| 4758989 | ROM having bit lines interlaced with column lines and cell column selection according to regularly interlaced logical fields | Harold L. Davis | 1988-07-19 |
| 4716380 | FET differential amplifier | — | 1987-12-29 |
| 4714840 | MOS transistor circuits having matched channel width and length dimensions | — | 1987-12-22 |
| 4649540 | Error-correcting circuit having a reduced syndrome word | — | 1987-03-10 |
| 4593214 | Circuit for discharging bootstrapped nodes in integrated circuits with the use of transistors designed to withstand only the normal voltage | — | 1986-06-03 |
| 4586170 | Semiconductor memory redundant element identification circuit | James E. O'Toole | 1986-04-29 |
| 4580067 | MOS dynamic load circuit for switching high voltages and adapted for use with high threshold transistors | Donald R. Dias | 1986-04-01 |
| 4573146 | Testing and evaluation of a semiconductor memory containing redundant memory elements | Andrew C. Graham, Dennis L. Segers | 1986-02-25 |
| 4510584 | MOS Random access memory cell with nonvolatile storage | Donald R. Dias, Daniel C. Guterman, Horst Leuschner | 1985-04-09 |