Issued Patents All Time
Showing 25 most recent of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7629820 | Delay circuit | Per Anders Johansson | 2009-12-08 |
| 7457392 | Delay locked loop | Christian Weis, Thomas J. Miller | 2008-11-25 |
| 7414445 | Device and method for the synchronization of clock signals and adjustment of the duty cycle of the clock signal | — | 2008-08-19 |
| 7404018 | Read latency control circuit | Stefan Dietrich, Thomas Hein, Peter Schroegmeier | 2008-07-22 |
| 7391245 | Delay locked loop and method for setting a delay chain | Aaron Nygren | 2008-06-24 |
| 7363561 | Method and circuit arrangement for resetting an integrated circuit | Stefan Dietrich, Thomas Hein, Peter Schrogmeier | 2008-04-22 |
| 7304515 | Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process | Martin Brox, Alessandro Minzoni, Rajashekhar Rao, Kazimierz Szczypinski | 2007-12-04 |
| 7126401 | Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device | Musa Saglam | 2006-10-24 |
| 7016452 | Delay locked loop | Torsten Partsch, Thomas Hein, Thilo Marx | 2006-03-21 |
| 6967893 | Integrated synchronous memory and memory configuration having a memory module with at least one synchronous memory | — | 2005-11-22 |
| 6928025 | Synchronous integrated memory | Thomas Hein, Thilo Marx, Torsten Partsch | 2005-08-09 |
| 6806752 | Method and logic/memory module for correcting the duty cycle of at least one control/reference signal | — | 2004-10-19 |
| 6784650 | Circuit configuration for generating a controllable output voltage | Thomas Hein, Thilo Marx, Torsten Partsch | 2004-08-31 |
| 6756820 | Optimized-delay multiplexer | Thoralf Gratz, Dieter Harle, Bret Johnson | 2004-06-29 |
| 6737901 | Integrable, controllable delay device, delay device in a control loop, and method for delaying a clock signal using a delay device | Thomas Hein | 2004-05-18 |
| 6670802 | Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits | Stefan Dietrich, Thilo Marx, Sabine Kieser, Michael Sommer, Thomas Hein +4 more | 2003-12-30 |
| 6661265 | Delay locked loop for generating complementary clock signals | Torsten Partsch, Thilo Marx, Thomas Hein | 2003-12-09 |
| 6657422 | Current mirror circuit | Thilo Marx, Thomas Hein, Torsten Partsch | 2003-12-02 |
| 6584021 | Semiconductor memory having a delay locked loop | Thomas Hein, Torsten Partsch, Marx Thilo | 2003-06-24 |
| 6573754 | Circuit configuration for enabling a clock signal in a manner dependent on an enable signal | Ullrich Menczigar | 2003-06-03 |
| 6542389 | Voltage pump with switch-on control | Stefan Dietrich, Thilo Marx, Sabine Kieser, Michael Sommer, Thomas Hein +4 more | 2003-04-01 |
| 6532188 | Integrated memory having a row access controller for activating and deactivating row lines | Stefan Dietrich, Thomas Hein, Thilo Marx, Torsten Partsch, Sabine Kieser +3 more | 2003-03-11 |
| 6529028 | Configuration for testing a plurality of memory chips on a wafer | Dieter Harle, Martin Buck | 2003-03-04 |
| 6480024 | Circuit configuration for programming a delay in a signal path | Stefan Dietrich, Thomas Hein, Michael Markert, Thilo Marx, Torsten Partsch +4 more | 2002-11-12 |
| 6472921 | Delivering a fine delay stage for a delay locked loop | Rajashekhar Rao | 2002-10-29 |