SD

Steven M. Douskey

IBM: 76 patents #914 of 70,183Top 2%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
📍 Rochester, MN: #55 of 3,042 inventorsTop 2%
🗺 Minnesota: #359 of 52,454 inventorsTop 1%
Overall (All Time): #23,854 of 4,157,543Top 1%
78
Patents All Time

Issued Patents All Time

Showing 26–50 of 78 patents

Patent #TitleCo-InventorsDate
9529046 Partitioned scan chain diagnostics using multiple bypass structures and injection points Michael J. Hamilton, Amanda R. Kaufer 2016-12-27
9429622 Implementing enhanced scan chain diagnostics via bypass multiplexing structure Michael J. Hamilton, Amanda R. Kaufer 2016-08-30
9429621 Implementing enhanced scan chain diagnostics via bypass multiplexing structure Michael J. Hamilton, Amanda R. Kaufer 2016-08-30
9404969 Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad dies Brion Keller, Mary P. Kusko 2016-08-02
9378318 Shared channel masks in on-product test compression system Mary P. Kusko 2016-06-28
9372232 Collecting diagnostic data from chips Ryan A. Fitch, William V. Huott, Mary P. Kusko 2016-06-21
9366723 Test coverage of integrated circuits with masking pattern selection Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer 2016-06-14
9355203 Shared channel masks in on-product test compression system Mary P. Kusko 2016-05-31
9297856 Implementing MISR compression methods for test time reduction Mary P. Kusko, Cedric Lichtenau 2016-03-29
9285423 Managing chip testing data Ryan A. Fitch, William V. Huott, Mary P. Kusko 2016-03-15
9201117 Managing redundancy repair using boundary scans Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer 2015-12-01
9188636 Self evaluation of system on a chip with multiple cores Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer 2015-11-17
9151800 Chip testing with exclusive OR Mary P. Kusko, Cedric Lichtenau 2015-10-06
9134373 Hierarchal test block test pattern reduction in on-product test compression system Mary P. Kusko 2015-09-15
9134375 Hierarchal test block test pattern reduction in on-product test compression system Mary P. Kusko 2015-09-15
9116205 Test coverage of integrated circuits with test vector input spreading Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer 2015-08-25
9110135 Chip testing with exclusive OR Mary P. Kusko, Cedric Lichtenau 2015-08-18
9103879 Test coverage of integrated circuits with test vector input spreading Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer 2015-08-11
9069041 Self evaluation of system on a chip with multiple cores Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer 2015-06-30
9032256 Multi-core processor comparison encoding Ryan A. Fitch, Michael J. Hamilton, Dennis Martin Rickert 2015-05-12
9003244 Dynamic built-in self-test system Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer 2015-04-07
8898530 Dynamic built-in self-test system Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer 2014-11-25
8868975 Testing and operating a multiprocessor chip with processor redundancy Ralph E. Bellofatto, Rudolf A. Haring, Moyra K. McManus, Martin Ohmacht, Dietmar Schmunkamp +2 more 2014-10-21
8856720 Test coverage of integrated circuits with masking pattern selection Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer 2014-10-07
8762803 Implementing enhanced pseudo random pattern generators with hierarchical linear feedback shift registers (LFSRs) Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer 2014-06-24