Issued Patents All Time
Showing 26–50 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9449134 | Dynamically reconfigurable logic circuits using native field-programmable gate array primitives | Roger Moussalli | 2016-09-20 |
| 9448845 | Extendible input/output data mechanism for accelerators | Parijat Dube, Hong Min, Donald W. Schmidt, Bharat Sukhwani, Mathew S. Thoennes | 2016-09-20 |
| 9336274 | Scalable acceleration of database query operations | Parijat Dube, Hong Min, Bharat Sukhwani, Mathew S. Thoennes | 2016-05-10 |
| 9336056 | Extendible input/output data mechanism for accelerators | Parijat Dube, Hong Min, Donald W. Schmidt, Bharat Sukhwani, Mathew S. Thoennes | 2016-05-10 |
| 9317497 | Offloading projection of fixed and variable length database columns | Parijat Dube, Hong Min, Bharat Sukhwani, Mathew S. Thoennes | 2016-04-19 |
| 9286423 | Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator | Mohit Kapur | 2016-03-15 |
| 9268879 | Hardware projection of fixed and variable length columns of database tables | Hong Min, Bharat Sukhwani, Mathew S. Thoennes | 2016-02-23 |
| 9251218 | Tunable hardware sort engine for performing composite sorting algorithms | Hong Min, Bharat Sukhwani, Mathew S. Thoennes | 2016-02-02 |
| 9251219 | Tunable hardware sort engine for performing composite sorting algorithms | Hong Min, Bharat Sukhwani, Mathew S. Thoennes | 2016-02-02 |
| 9235564 | Offloading projection of fixed and variable length database columns | Parijat Dube, Hong Min, Bharat Sukhwani, Mathew S. Thoennes | 2016-01-12 |
| 9177006 | Radix sort with read-only key | Hong Min, Bharat Sukhwani, Mathew S. Thoennes | 2015-11-03 |
| 9171032 | Radix sort with read-only key | Hong Min, Bharat Sukhwani, Mathew S. Thoennes | 2015-10-27 |
| 9081501 | Multi-petascale highly efficient parallel supercomputer | Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto +55 more | 2015-07-14 |
| 9002693 | Wire like link for cycle reproducible and cycle accurate hardware accelerator | Mohit Kapur, Benjamin D. Parker | 2015-04-07 |
| 8983992 | Facilitating field programmable gate array accelerations of database functions | Bernard V. Brezzo, Donna N. Dillenberger, Parijat Dube, Balakrishna Raghavendra Iyer, Hong Min +2 more | 2015-03-17 |
| 8977637 | Facilitating field programmable gate array accelerations of database functions | Bernard V. Brezzo, Donna N. Dillenberger, Parijat Dube, Balakrishna Raghavendra Iyer, Hong Min +2 more | 2015-03-10 |
| 8838577 | Accelerated row decompression | Bharat Sukhwani, Balakrishna Raghavendra Iyer, Hong Min, Mathew S. Thoennes | 2014-09-16 |
| 8805850 | Hardware-accelerated relational joins | Bharat Sukhwani, Hong Min, Mathew S. Thoennes, Gong Su | 2014-08-12 |
| 8788512 | Generating data feed specific parser circuits | Roger Moussalli, Bharat Sukhwani | 2014-07-22 |
| 8737233 | Increasing throughput of multiplexed electrical bus in pipe-lined architecture | Bernard V. Brezzo, Mohit Kapur | 2014-05-27 |
| 8640070 | Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs) | Ralph E. Bellofatto, Bernard V. Brezzo, Charles L. Haymes, Mohit Kapur, Benjamin D. Parker +2 more | 2014-01-28 |
| 8108838 | System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture | Richard Gerard Hofmann | 2012-01-31 |
| 7523449 | System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture | Richard Gerard Hofmann | 2009-04-21 |
| 7167971 | System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture | Richard Gerard Hofmann | 2007-01-23 |
| 7130963 | System and method for instruction memory storage and processing based on backwards branch control information | Jaime Moreno, Jude A. Rivers, John-David Wellman | 2006-10-31 |