Issued Patents All Time
Showing 26–50 of 102 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9098351 | Energy-aware job scheduling for cluster environments | Luigi Brochard, Donald R. DeSota, Rajendra D. Panda, Francois Thomas | 2015-08-04 |
| 9065840 | Determining server write activity levels to use to adjust write cache size | Michael D. Roll, Olga Yiparaki | 2015-06-23 |
| 9009406 | Determining server write activity levels to use to adjust write cache size | Michael D. Roll, Olga Yiparaki | 2015-04-14 |
| 8959286 | Hybrid storage subsystem with mixed placement of file contents | Men-Chow Chiang, Hong Hua, Mysore S. Srinivas | 2015-02-17 |
| 8943272 | Variable cache line size management | Wen-Tzer T. Chen, Diane G. Flemming, Hong Hua, William A. Maron, Mysore S. Srinivas | 2015-01-27 |
| 8935478 | Variable cache line size management | Wen-Tzer T. Chen, Diane G. Flemming, Hong Hua, William A. Maron, Mysore S. Srinivas | 2015-01-13 |
| 8898674 | Memory databus utilization management system and computer program product | Donald R. DeSota, Rajendra D. Panda, Venkat R. Indukuru, Joseph H. Robichaux, Steven Paul Hartman | 2014-11-25 |
| 8886918 | Dynamic instruction execution based on transaction priority tagging | Louis Bennie Capps, Jr. | 2014-11-11 |
| 8812321 | System and method for combining speech recognition outputs from a plurality of domain-specific speech recognizers via machine learning | Mazin Gilbert, Srinivas Bangalore, Patrick Haffner | 2014-08-19 |
| 8806153 | Partial line cache write injector for direct memory access write | Herman Dietrich Dierks, Jr., Hong Hua, Mysore S. Srinivas | 2014-08-12 |
| 8782346 | Dynamic prioritization of cache access | Hong Hua, William A. Maron, Mysore S. Srinivas | 2014-07-15 |
| 8769210 | Dynamic prioritization of cache access | Hong Hua, William A. Maron, Mysore S. Srinivas | 2014-07-01 |
| 8751751 | Method and apparatus for minimizing cache conflict misses | Men-Chow Chiang, Hong Hua | 2014-06-10 |
| 8745362 | Operating system aware branch predictor using a dynamically reconfigurable branch history table | Wen-Tzer T. Chen | 2014-06-03 |
| 8713287 | Off-loading of processing from a processor blade to storage blades based on processing activity, availability of cache, and other status indicators | Jose R. Escalera, Octavian F. Herescu, Vernon W. Miller, Sergio Reyes, Michael D. Roll | 2014-04-29 |
| 8694732 | Enhanced coherency tracking with implementation of region victim hash for region coherence arrays | Jason F. Cantin | 2014-04-08 |
| 8688960 | Managing migration of a prefetch stream from one processor core to another processor core | Matthew Accapadi, Hong Hua, Ram Raghavan, Mysore S. Srinivas | 2014-04-01 |
| 8688961 | Managing migration of a prefetch stream from one processor core to another processor core | Matthew Accapadi, Hong Hua, Ram Raghavan, Mysore S. Srinivas | 2014-04-01 |
| 8645673 | Multicore processor and method of use that adapts core functions based on workload execution | Louis Bennie Capps, Jr., Thomas E. Cook, Glenn G. Daves, Ronald E. Newhart, Michael A. Paolini +1 more | 2014-02-04 |
| 8612984 | Energy-aware job scheduling for cluster environments | Luigi Brochard, Donald R. DeSota, Rajendra D. Panda, Francois Thomas | 2013-12-17 |
| 8544006 | Resolving conflicts by restarting execution of failed discretely executable subcomponent using register and memory values generated by main component after the occurrence of a conflict | Louis Bennie Capps, Jr., Michael A. Paolini, Michael J. Shapiro | 2013-09-24 |
| 8527956 | Workload performance projection via surrogate program analysis for future information handling systems | Luigi Brochard, Donald R. DeSota, Venkat R. Indukuru, Rajendra D. Panda, Sameh S. Sharkawi | 2013-09-03 |
| 8527997 | Energy-aware job scheduling for cluster environments | Luigi Brochard, Donald R. DeSota, Rajendra D. Panda, Francois Thomas | 2013-09-03 |
| 8515882 | Efficient storage of individuals for optimization simulation | Jason F. Cantin | 2013-08-20 |
| 8495342 | Configuring plural cores to perform an instruction having a multi-core characteristic | Louis Bennie Capps, Jr., Michael J. Shapiro, Thomas E. Cook, William E. Burky | 2013-07-23 |