| 10169087 |
Technique for preserving memory affinity in a non-uniform memory access data processing system |
Mathew Accapadi, Robert H. Bell, Jr., Hong Hua |
2019-01-01 |
| 9727469 |
Performance-driven cache line memory access |
Robert H. Bell, Jr., Hong Hua, Mysore S. Srinivas |
2017-08-08 |
| 9626294 |
Performance-driven cache line memory access |
Robert H. Bell, Jr., Hong Hua, Mysore S. Srinivas |
2017-04-18 |
| 9378069 |
Lock spin wait operation for multi-threaded applications in a multi-core computing environment |
Ken V. Vu |
2016-06-28 |
| 8959286 |
Hybrid storage subsystem with mixed placement of file contents |
Robert H. Bell, Jr., Hong Hua, Mysore S. Srinivas |
2015-02-17 |
| 8751751 |
Method and apparatus for minimizing cache conflict misses |
Robert H. Bell, Jr., Hong Hua |
2014-06-10 |
| 8438334 |
Hybrid storage subsystem with mixed placement of file contents |
Robert H. Bell, Jr., Hong Hua, Mysore S. Srinivas |
2013-05-07 |
| 8413158 |
Processor thread load balancing manager |
Hong Hua |
2013-04-02 |
| 8402470 |
Processor thread load balancing manager |
Hong Hua |
2013-03-19 |
| 8146087 |
System and method for enabling micro-partitioning in a multi-threaded processor |
Sujatha Kashyap, Mysore S. Srinivas |
2012-03-27 |
| 7783858 |
Reducing memory overhead of a page table in a dynamic logical partitioning environment |
Kiet H. Lam |
2010-08-24 |
| 7318125 |
Runtime selective control of hardware prefetch mechanism |
Kaivalya M. Dixit, Sujatha Kashyap |
2008-01-08 |
| 7117337 |
Apparatus and method for providing pre-translated segments for page translations in segmented operating systems |
Sujatha Kashyap |
2006-10-03 |
| 7107431 |
Apparatus and method for lazy segment promotion for pre-translated segments |
Sujatha Kashyap |
2006-09-12 |