Issued Patents All Time
Showing 26–44 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7451231 | Data processing system, method and interconnect fabric for synchronized communication in a data processing system | Benjiman L. Goodman, Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli | 2008-11-11 |
| 7430684 | Method to use fabric initialization to test functionality of all inter-chip paths between processors in system | Benjiman L. Goodman, Paul Frank Lecocq | 2008-09-30 |
| 7415030 | Data processing system, method and interconnect fabric having an address-based launch governor | Benjiman L. Goodman, Jeffrey A. Stuecheli | 2008-08-19 |
| 7380102 | Communication link control among inter-coupled multiple processing units in a node to respective units in another node for request broadcasting and combined response | Vicente Enrique Chung, Benjiman L. Goodman, William J. Starke | 2008-05-27 |
| 7085847 | Method and system for scheduling network communication | B. Scott Darnell, William T. Jennings, Bradley D. Lengel | 2006-08-01 |
| 6725307 | Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system | Manuel J. Alvarez, II, Joel Roger Davidson, Sanjay Deshpande, Peter Geiger, Lawrence Powell | 2004-04-20 |
| 6678814 | Method and apparatus for allocating data usages within an embedded dynamic random access memory device | Ravi Kumar Arimilli, James Stephen Fields, Jr., Sanjeev Ghai, William J. Starke | 2004-01-13 |
| 6606680 | Method and apparatus for accessing banked embedded dynamic random access memory devices | Ravi Kumar Arimilli, James Stephen Fields, Jr., Sanjeev Ghai, William J. Starke | 2003-08-12 |
| 6574719 | Method and apparatus for concurrently communicating with multiple embedded dynamic random access memory devices | Ravi Kumar Arimilli, James Stephen Fields, Jr., Sanjeev Ghai, William J. Starke | 2003-06-03 |
| 6553463 | Method and system for high speed access to a banked cache memory | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, James Stephen Fields, Jr., Sanjeev Ghai | 2003-04-22 |
| 6539487 | System for dynamically selecting maximum number of accessible banks of memory per cycle by monitoring actual power to each of the banks to determine the number of accessible banks | James Stephen Fields, Jr., Sanjeev Ghai | 2003-03-25 |
| 6467030 | Method and apparatus for forwarding data in a hierarchial cache memory architecture | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr., Sanjeev Ghai | 2002-10-15 |
| 6457085 | Method and system for data bus latency reduction using transfer size prediction for split bus designs | — | 2002-09-24 |
| 6449698 | Method and system for bypass prefetch data path | Sanjay Deshpande, David Mui | 2002-09-10 |
| 6381647 | Method and system for scheduling network communication | B. Scott Darnell, William T. Jennings, Bradley D. Lengel | 2002-04-30 |
| 6374314 | METHOD FOR MANAGING STORAGE OF DATA BY STORING BUFFER POINTERS OF DATA COMPRISING A SEQUENCE OF FRAMES IN A MEMORY LOCATION DIFFERENT FROM A MEMORY LOCATION FOR POINTERS OF DATA NOT COMPRISING A SEQUENCE OF FRAMES | B. Scott Darnell, William T. Jennings, Bradley D. Lengel | 2002-04-16 |
| 6317415 | Method and system for communicating information in a network | B. Scott Darnell, William T. Jennings, Bradley D. Lengel | 2001-11-13 |
| 6298416 | Method and apparatus for transmitting control signals within a hierarchial cache memory architecture for a data processing system | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr., Sanjeev Ghai | 2001-10-02 |
| 6266702 | Method and apparatus to insert and extract data from a plurality of slots of data frames by using access table to identify network nodes and their slots for insertion and extraction data | B. Scott Darnell, William T. Jennings, Bradley D. Lengel | 2001-07-24 |