Issued Patents All Time
Showing 51–66 of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7443180 | On-chip probing apparatus | Daniel N. de Araujo, Bradley D. Herrman, Erdem Matoglu, Bhyrav M. Mutnury, Pravin Patel +1 more | 2008-10-28 |
| 7444490 | Apparatus, system, and method for modifying memory voltage and performance based on a measure of memory device stress | Daniel N. de Araujo, Nam H. Pham, Menas Roumbakis | 2008-10-28 |
| 7394281 | Bi-directional universal serial bus booster circuit | Justin P. Bandholz, Bradley D. Herman, Erdem Matoglu, Bhyrav M. Mutnury, Thomas D. Pahel, Jr. +3 more | 2008-07-01 |
| 6600347 | Dynamically producing an effective impedance of an output driver with a bounded variation during transitions thereby reducing jitter | John Michael Borkenhagen, Daniel M. Dreps, David LeRoy Guertin, Nam H. Pham, Robert R. Williams | 2003-07-29 |
| 6279142 | Method of on-chip interconnect design | Michael Alexander Bowen, Howard H. Smith | 2001-08-21 |
| 5986472 | Voltage level translation for an output driver system with a bias generator | Fahd Hinedi, Satyajit Dutta, Robert H. Dennard | 1999-11-16 |
| 5905618 | Voltage protected level shifting of chip driver | Satyajit Dutta, Fahd Hinedi | 1999-05-18 |
| 5867010 | Circuit and method for voltage level translation utilizing a bias generator | Fahd Hinedi, Satyajit Dutta, Robert H. Dennard | 1999-02-02 |
| 5828259 | Method and apparatus for reducing disturbances on an integrated circuit | Leon L. Wu | 1998-10-27 |
| 5777490 | Circuitry and method for translating voltages | Fahd Hinedi | 1998-07-07 |
| 5621902 | Computer system having a bridge between two buses with a direct memory access controller and an alternative memory access controller | Richard Gerard Hofmann, Lance M. Venarchick | 1997-04-15 |
| 5517650 | Bridge for a power managed computer system with multiple buses and system arbitration | Patrick M. Bland, Richard Gerard Hofmann, Dennis Moeller, Suksoon Yong, Lance M. Venarchick +1 more | 1996-05-14 |
| 4583193 | Integrated circuit mechanism for coupling multiple programmable logic arrays to a common bus | Wayne R. Kraft, William L. Stahl, Jr., Nandor G. Thoma, Virgil D. Wyatt | 1986-04-15 |
| 4575794 | Clocking mechanism for multiple overlapped dynamic programmable logic arrays used in a digital control unit | Gerard A. Veneski, Nandor G. Thoma | 1986-03-11 |
| 4500800 | Logic performing cell for use in array structures | Wayne R. Kraft, William L. Stahl, Jr., Nandor G. Thoma | 1985-02-19 |
| 4395646 | Logic performing cell for use in array structures | Wayne R. Kraft, Victor S. Moore, William L. Stahl, Jr., Nandor G. Thoma | 1983-07-26 |