Issued Patents All Time
Showing 26–50 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8868837 | Cache directory lookup reader set encoding for partial cache line speculation support | Alan Gara | 2014-10-21 |
| 8856490 | Optimizing TLB entries for mixed page size storage in contiguous memory | Dong Chen, Alan Gara, Mark E. Giampapa, Philip Heidelberger, Jon K. Kriegel +1 more | 2014-10-07 |
| 8838906 | Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution | Alan Gara | 2014-09-16 |
| 8838944 | Fast concurrent array-based stacks, queues and deques using fetch-and-increment-bounded, fetch-and-decrement-bounded and store-on-twin synchronization primitives | Dong Chen, Alana Gara, Philip Heidelberger, Sameer Kumar, Burkhard Steinmacher-Burow +1 more | 2014-09-16 |
| 8832403 | Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses | — | 2014-09-09 |
| 8832415 | Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests | Alan Gala | 2014-09-09 |
| 8806141 | List based prefetch | Peter Boyle, Norman Christ, Alan Gara, Changhoan Kim, Robert Mawhinney +1 more | 2014-08-12 |
| 8788879 | Non-volatile memory for checkpoint storage | Matthias A. Blumrich, Dong Chen, Thomas M. Cipolla, Paul W. Coteus, Alan Gara +4 more | 2014-07-22 |
| 8756350 | Method and apparatus for efficiently tracking queue entries relative to a timestamp | Matthias A. Blumrich, Dong Chen, Alan Gara, Mark E. Giampapa, Philip Heidelberger +2 more | 2014-06-17 |
| 8751748 | Reader set encoding for directory of shared cache memory in multiprocessor system | Daniel Ahn, Luis Ceze, Alan Gara, Zhuang Xiaotong | 2014-06-10 |
| 8677073 | Snoop filter for filtering snoop requests | Matthias A. Blumrich, Dong Chen, Alan Gara, Mark E. Giampapa, Philip Heidelberger +3 more | 2014-03-18 |
| 8627010 | Write-through cache optimized for dependence-free parallel regions | Alexandre E. Eichenberger, Alan Gara, Vijayalakshmi Srinivasan | 2014-01-07 |
| 8621478 | Multiprocessor system with multiple concurrent modes of execution | Daniel Ahn, Luis Ceze, Dong Chen, Alan Gara, Philip Heidelberger | 2013-12-31 |
| 8595554 | Reproducibility in a multiprocessor system | Ralph A. Bellofatto, Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara +9 more | 2013-11-26 |
| 8533399 | Cache directory look-up re-use as conflict check mechanism for speculative memory requests | — | 2013-09-10 |
| 8521961 | Checkpointing in speculative versioning caches | Alexandre E. Eichenberger, Alan Gara, Michael K. Gschwind | 2013-08-27 |
| 8516197 | Write-through cache optimized for dependence-free parallel regions | Alexandre E. Eichenberger, Alan Gara, Vijayalakshmi Srinivasan | 2013-08-20 |
| 8473683 | Ordering of guarded and unguarded stores for no-sync I/O | Alan Gara | 2013-06-25 |
| 8468416 | Combined group ECC protection and subgroup parity protection | Alan Gara, Dong Chen, Philip Heidelberger | 2013-06-18 |
| 8458282 | Extended write combining using a write continuation hint flag | Dong Chen, Alan Gara, Philip Heidelberger, Pavlos M. Vranas | 2013-06-04 |
| 8447960 | Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition | Dong Chen, Mark E. Giampapa, Philip Heidelberger, David L. Satterfield, Burkhard Steinmacher-Burow +1 more | 2013-05-21 |
| 8429377 | Optimizing TLB entries for mixed page size storage in contiguous memory | Dong Chen, Alan Gara, Mark E. Giampapa, Philip Heidelberger, Jon K. Kriegel +1 more | 2013-04-23 |
| 8412974 | Global synchronization of parallel processors using clock pulse width modulation | Dong Chen, Matthew R. Ellavsky, Ross L. Franke, Alan Gara, Thomas M. Gooding +8 more | 2013-04-02 |
| 8397052 | Version pressure feedback mechanisms for speculative versioning caches | Alexandre E. Eichenberger, Alan Gara, Kathryn M. O'Brien, Xiaotong Zhuang | 2013-03-12 |
| 8370551 | Arbitration in crossbar interconnect for low latency | Krishnan Sugavanam | 2013-02-05 |