Issued Patents All Time
Showing 151–175 of 190 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7336554 | Semiconductor memory device having a reduced number of pins | Chang Hyun Kim | 2008-02-26 |
| 7269078 | Buffer circuit and memory system for selectively outputting data strobe signal according to number of data bits | Sung-Min Seo, Chul Soo Kim, Jin-Kyoung Jung | 2007-09-11 |
| 7212052 | Jitter suppressing delay locked loop circuits and related methods | — | 2007-05-01 |
| 7199634 | Duty cycle correction circuits suitable for use in delay-locked loops and methods of correcting duty cycles of periodic signals | Geun-Hee Cho | 2007-04-03 |
| 7199630 | Delay locked loops and methods using ring oscillators | — | 2007-04-03 |
| 7190206 | Interface circuit and signal clamping circuit using level-down shifter | Jae Hyung Lee | 2007-03-13 |
| 7184509 | Delay locked loop circuit for internally correcting duty cycle and duty cycle correction method thereof | Geun-Hee Cho | 2007-02-27 |
| 7135935 | Hyper-ring oscillator | — | 2006-11-14 |
| 7133318 | Output driver capable of controlling slew rate of output signal according to operating frequency information or CAS latency information | Hoe-Ju Chung | 2006-11-07 |
| 7123520 | Buffer circuit and memory system for selectively outputting data strobe signal according to number of data bits | Sung-Min Seo, Chul Soo Kim, Jin-Kyoung Jung | 2006-10-17 |
| 7091741 | Input buffer capable of reducing input capacitance seen by input signal | — | 2006-08-15 |
| 7085336 | Signal transmission circuit and method for equalizing disparate delay times dynamically, and data latch circuit of semiconductor device implementing the same | Jung-Bae Lee | 2006-08-01 |
| 7057433 | Delay-Locked Loop (DLL) capable of directly receiving external clock signals | Guen-Hee Cho | 2006-06-06 |
| 7038972 | Double data rate synchronous dynamic random access memory semiconductor device | Sung-Min Seo, Chi-Wook Kim | 2006-05-02 |
| 7035148 | Output driver capable of controlling slew rate of output signal according to operating frequency information or CAS latency information | Hoe-Ju Chung | 2006-04-25 |
| 7015739 | Integrated circuit devices having duty cycle correction circuits that receive control signals over first and second separate paths and methods of operating the same | Woo Jin Lee | 2006-03-21 |
| 6999375 | Synchronous semiconductor device and method of preventing coupling between data buses | Jin-Kyoung Jung | 2006-02-14 |
| 6980036 | Semiconductor device comprising frequency multiplier of external clock and output buffer of test data and semiconductor test method | Kyoung-Hwan Kwon, Hyun-Soon Jang | 2005-12-27 |
| 6954094 | Semiconductor memory device having partially controlled delay locked loop | Jae Hyung Lee | 2005-10-11 |
| 6934215 | Semiconductor memory device having duty cycle correction circuit and interpolation circuit interpolating clock signal in the semiconductor memory device | Hoe-Ju Chung | 2005-08-23 |
| 6870776 | Data output circuit in combined SDR/DDR semiconductor memory device | Chul Soo Kim | 2005-03-22 |
| 6853317 | Circuit and method for generating mode register set code | Chul Soo Kim | 2005-02-08 |
| 6847559 | Input buffer circuit of a synchronous semiconductor memory device | Reum Oh, Woo-Seop Jeong | 2005-01-25 |
| 6812765 | Pulsed signal transition delay adjusting circuit | Dae-Hyun Chung | 2004-11-02 |
| 6734707 | Data input circuit for reducing loading difference between fetch signal and multiple data in semiconductor device | Ho-Young Song, Su Bong Jang | 2004-05-11 |