Issued Patents All Time
Showing 76–100 of 190 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9224450 | Reference voltage modification in a memory device | Edgar R. Cordero, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow | 2015-12-29 |
| 9196347 | DRAM controller for variable refresh operation timing | Hillery C. Hunter, Janani Mukundan | 2015-11-24 |
| 9189327 | Error-correcting code distribution for memory systems | Paul W. Coteus, Hillery C. Hunter, Charles A. Kilmer, Warren E. Maule, Kenneth L. Wright | 2015-11-17 |
| 9159410 | Accessing a resistive memory storage device | Charles A. Kilmer, Warren E. Maule | 2015-10-13 |
| 9146883 | Securing the contents of a memory device | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Luis A. Lastras-Montano +1 more | 2015-09-29 |
| 9146882 | Securing the contents of a memory device | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Luis A. Lastras-Montano +1 more | 2015-09-29 |
| 9087612 | DRAM error detection, evaluation, and correction | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Luis A. Lastras-Montano +1 more | 2015-07-21 |
| 9076770 | Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same | Jimmy G. Foster, Sr. | 2015-07-07 |
| 9064602 | Implementing memory device with sub-bank architecture | Hillery C. Hunter, Charles A. Kilmer, Warren E. Maule | 2015-06-23 |
| 9058896 | DRAM refresh | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Luis A. Lastras +1 more | 2015-06-16 |
| 9053811 | Memory device refresh | Paul W. Coteus, Douglas J. Joseph | 2015-06-09 |
| 9037930 | Managing errors in a DRAM by weak cell encoding | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Luis A. Lastras-Montano +1 more | 2015-05-19 |
| 9001609 | Hybrid latch and fuse scheme for memory repair | Michele M. Franceschini, Hillery C. Hunter, Charles A. Kilmer, Luis A. Lastras-Montano | 2015-04-07 |
| 8995217 | Hybrid latch and fuse scheme for memory repair | Michele M. Franceschini, Hillery C. Hunter, Charles A. Kilmer, Luis A. Lastras-Montano | 2015-03-31 |
| 8909878 | Implementing timing alignment and synchronized memory activities of multiple memory devices accessed in parallel | Paul W. Coteus | 2014-12-09 |
| 8898544 | DRAM error detection, evaluation, and correction | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Luis A. Lastras-Montano +1 more | 2014-11-25 |
| 8890316 | Implementing decoupling devices inside a TSV DRAM stack | Joab D. Henderson, Warren E. Maule, Kenneth L. Wright | 2014-11-18 |
| 8887014 | Managing errors in a DRAM by weak cell encoding | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Luis A. Lastras-Montano +1 more | 2014-11-11 |
| 8856579 | Memory interface having extended strobe burst for read timing calibration | Kevin C. Gower | 2014-10-07 |
| 8848471 | Method for optimizing refresh rate for DRAM | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Luis A. Lastras +1 more | 2014-09-30 |
| 8823162 | Integrated circuit die stacks with translationally compatible vias | Jimmy G. Foster, Sr. | 2014-09-02 |
| 8824573 | Digital phase detector with zero phase offset | Daniel M. Dreps, Glen A. Wiedemeier | 2014-09-02 |
| 8816490 | Integrated circuit die stacks with rotationally symmetric VIAS | Jimmy G. Foster, Sr. | 2014-08-26 |
| 8797823 | Implementing SDRAM having no RAS to CAS delay in write operation | Brian J. Connolly, Warren E. Maule | 2014-08-05 |
| 8799566 | Memory system with a programmable refresh cycle | Charles A. Kilmer, Warren E. Maule, Vipin Patel | 2014-08-05 |