Issued Patents All Time
Showing 51–75 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8921199 | Precision IC resistor fabrication | Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams | 2014-12-30 |
| 8895436 | Implementing enhanced power supply distribution and decoupling utilizing TSV exclusion zone | Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams | 2014-11-25 |
| 8816470 | Independently voltage controlled volume of silicon on a silicon on insulator chip | Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams | 2014-08-26 |
| 8754499 | Semiconductor chip with power gating through silicon vias | Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams | 2014-06-17 |
| 8735975 | Implementing semiconductor soc with metal via gate node high performance stacked transistors | Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams | 2014-05-27 |
| 8617939 | Enhanced thin film field effect transistor integration into back end of line | Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams | 2013-12-31 |
| 8592921 | Deep trench embedded gate transistor | Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Ulmann, Kelly L. Williams | 2013-11-26 |
| 8574982 | Implementing eDRAM stacked FET structure | David P. Paulsen, John E. Sheets, II, Kelly L. Williams | 2013-11-05 |
| 8575613 | Implementing vertical signal repeater transistors utilizing wire vias as gate nodes | Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams | 2013-11-05 |
| 8525245 | eDRAM having dynamic retention and performance tradeoff | Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams | 2013-09-03 |
| 8492207 | Implementing eFuse circuit with enhanced eFuse blow operation | Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams | 2013-07-23 |
| 8492220 | Vertically stacked FETs with series bipolar junction transistor | Phil C. Paone, David P. Paulsen, John E. Sheets, II, Kelly L. Williams | 2013-07-23 |
| 8456187 | Implementing temporary disable function of protected circuitry by modulating threshold voltage of timing sensitive circuit | Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams | 2013-06-04 |
| 8435851 | Implementing semiconductor SoC with metal via gate node high performance stacked transistors | Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams | 2013-05-07 |
| 8395186 | Implementing vertical signal repeater transistors utilizing wire vias as gate nodes | Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams | 2013-03-12 |
| 8384414 | Implementing hacking detection and block function at indeterminate times with priorities and limits | Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams | 2013-02-26 |
| 7915949 | Implementing eFuse resistance determination before initiating eFuse blow | Phil C. Paone, David P. Paulsen, John E. Sheets, II | 2011-03-29 |
| 7696565 | FinFET body contact structure | Richard Lee Donze, William Paul Hovis, Terrance Wayne Kueper, John E. Sheets, II, Jon Robert Tetzloff | 2010-04-13 |
| 7659733 | Electrical open/short contact alignment structure for active region vs. gate region | Richard Lee Donze, William Paul Hovis, John Edward Sheet, II, Jon Robert Tetzloff | 2010-02-09 |
| 7551470 | Non volatile memory RAD-hard (NVM-rh) system | John A. Fifield, Chandrasekara Kothandaraman, Phil C. Paone, William R. Tonti | 2009-06-23 |
| 7550789 | Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable | Anthony R. Bonaccio, John A. Fifield, Chandrasekharan Kothandaraman, Phil C. Paone, William R. Tonti | 2009-06-23 |
| 7453272 | Electrical open/short contact alignment structure for active region vs. gate region | Richard Lee Donze, William Paul Hovis, John E. Sheets, II, Jon Robert Tetzloff | 2008-11-18 |
| 7442583 | Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable | Anthony R. Bonaccio, John A. Fifield, Chandrasekharan Kothandaraman, Phil C. Paone, William R. Tonti | 2008-10-28 |
| 7336095 | Changing chip function based on fuse states | John A. Fifield, Chandrasekharan Kothandaraman, Phil C. Paone, William R. Tonti | 2008-02-26 |
| 7336086 | Measurement of bias of a silicon area using bridging vertices on polysilicon shapes to create an electrical open/short contact structure | Richard Lee Donze, William Paul Hovis, John E. Sheets, II, Jon Robert Tetzloff | 2008-02-26 |