Issued Patents All Time
Showing 101–125 of 192 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9786756 | Self-aligned source and drain regions for semiconductor devices | Joel P. de Souza, Bahman Hekmatshoartabari, Siegfried Maurer, Devendra K. Sadana | 2017-10-10 |
| 9768254 | Leakage-free implantation-free ETSOI transistors | Joel P. de Souza, Keith E. Fogel, Devendra K. Sadana | 2017-09-19 |
| 9748412 | Highly responsive III-V photodetectors using ZnO:Al as N-type emitter | Ning Li, Devendra K. Sadana, Brent A. Wacaser | 2017-08-29 |
| 9741880 | Three-dimensional conductive electrode for solar cell | Keith E. Fogel, Augustin J. Hong, Devendra K. Sadana | 2017-08-22 |
| 9741890 | Protective insulating layer and chemical mechanical polishing for polycrystalline thin film solar cells | Talia S. Gershon, Supratik Guha, Mahadevaiyer Krishnan, Byungha Shin | 2017-08-22 |
| 9722120 | Bandgap grading of CZTS solar cell | Talia S. Gershon, Marinus Hopstaken, Yun Seog Lee | 2017-08-01 |
| 9722033 | Doped zinc oxide as n+ layer for semiconductor devices | Joel P. Desouza, Keith E. Fogel, Ko-Tao Lee, Devendra K. Sadana | 2017-08-01 |
| 9716195 | Dry etch method for texturing silicon and device | Talia S. Gershon, Richard A. Haight, Yun Seog Lee | 2017-07-25 |
| 9716207 | Low reflection electrode for photovoltaic devices | Keith E. Fogel, David B. Mitzi, Mark T. Winkler | 2017-07-25 |
| 9691847 | Self-formation of high-density arrays of nanostructures | Christos D. Dimitrakopoulos, Hongsik Park, Byungha Shin | 2017-06-27 |
| 9673290 | Self-aligned source and drain regions for semiconductor devices | Joel P. de Souza, Bahman Hekmatshoartabari, Siegfried Maurer, Devendra K. Sadana | 2017-06-06 |
| 9666674 | Formation of large scale single crystalline graphene | Christos D. Dimitrakopoulos, Keith E. Fogel, Hongsik Park | 2017-05-30 |
| 9660116 | Nanowires formed by employing solder nanodots | Keith E. Fogel, Jae-Woong Nah, Devendra K. Sadana, Kuen-Ting Shiu | 2017-05-23 |
| 9653570 | Junction interlayer dielectric for reducing leakage current in semiconductor devices | Joel P. de Souza, Keith E. Fogel, Devendra K. Sadana, Brent A. Wacaser | 2017-05-16 |
| 9646832 | Porous fin as compliant medium to form dislocation-free heteroepitaxial films | Kangguo Cheng, Keith E. Fogel, Devendra K. Sadana | 2017-05-09 |
| 9634164 | Reduced light degradation due to low power deposition of buffer layer | Keith E. Fogel, Augustin J. Hong, Devendra K. Sadana | 2017-04-25 |
| 9620592 | Doped zinc oxide and n-doping to reduce junction leakage | Joel P. de Souza, Keith E. Fogel, Siegfried Maurer, Devendra K. Sadana | 2017-04-11 |
| 9607952 | High-z oxide nanoparticles embedded in semiconductor package | Qing Cao, Ying He, Ning Li | 2017-03-28 |
| 9601583 | Hetero-integration of III-N material on silicon | Can Bayram, Christopher P. D'Emic, Devendra K. Sadana | 2017-03-21 |
| 9583562 | Reduction of defect induced leakage in III-V semiconductor devices | Joel P. de Souza, Devendra K. Sadana, Brent A. Wacaser | 2017-02-28 |
| 9577196 | Optoelectronics integration by transfer process | Ning Li, Devendra K. Sadana, Tze-bin Song | 2017-02-21 |
| 9574287 | Gallium nitride material and device deposition on graphene terminated wafer and method of forming the same | Can Bayram, Christos D. Dimitrakopoulos, Keith E. Fogel, John A. Ott, Devendra K. Sadana | 2017-02-21 |
| 9559120 | Porous silicon relaxation medium for dislocation free CMOS devices | Kangguo Cheng, Ramachandra Divakaruni, Juntao Li, Devendra K. Sadana | 2017-01-31 |
| 9537038 | Solar cell made using a barrier layer between P-type and intrinsic layers | Tze-Chiang Chen, Augustin J. Hong, Chien-Chih Huang, Yu-Wei Huang, Devendra K. Sadana +1 more | 2017-01-03 |
| 9536945 | MOSFET with ultra low drain leakage | Joel P. de Souza, Keith E. Fogel, Devendra K. Sadana | 2017-01-03 |