Issued Patents All Time
Showing 1–25 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430485 | VLSI placement optimization using self-supervised graph clustering | Yi-Chen Lu, Tian Yang | 2025-09-30 |
| 12417334 | Lithography simulation using a neural network | Haoyu Yang, Zongyi Li | 2025-09-16 |
| 12412082 | Fine-grained per-vector scaling for neural network quantization | Brucek Kurdo Khailany, Steve Haihang Dai, Rangharajan Venkatesan | 2025-09-09 |
| 12373622 | Reducing crosstalk pessimism using GPU-accelerated gate simulation and machine learning | Vidya Chhabria, Benjamin Andrew Keller, Yanqing Zhang, Brucek Kurdo Khailany | 2025-07-29 |
| 12277376 | Rail power density aware standard cell placement for integrated circuits | Shaurakar Das, Santosh Santosh, SeshasaiJyothi Kolli, Muhammad Arif Mirza, Sreedhar Pratty | 2025-04-15 |
| 12217151 | Layout parasitics and device parameter prediction using graph neural networks | George Ferenc Kokai, Ting Ku, Walker Joseph Turner | 2025-02-04 |
| 12169677 | Standard cell layout generation with applied artificial intelligence | Matthew Rudolph Fojtik | 2024-12-17 |
| 12045307 | Fine-grained per-vector scaling for neural network quantization | Brucek Kurdo Khailany, Steve Haihang Dai, Rangharajan Venkatesan | 2024-07-23 |
| 12019967 | Routing connections in integrated circuits based on reinforcement learning | Matthew Rudolph Fojtik | 2024-06-25 |
| 11972188 | Rail power density aware standard cell placement for integrated circuits | Shaurakar Das, Santosh Santosh, SeshasaiJyothi Kolli, Muhammad Arif Mirza, Sreedhar Pratty | 2024-04-30 |
| 11651194 | Layout parasitics and device parameter prediction using graph neural networks | George Ferenc Kokai, Ting Ku, Walker Joseph Turner | 2023-05-16 |
| 11645533 | IR drop prediction with maximum convolutional neural network | Zhiyao Xie, Brucek Kurdo Khailany, Sheng Ye | 2023-05-09 |
| 10956644 | Integrated circuit design changes using through-silicon vias | Harry Barowski, Joachim Keinert, Sridhar H. Rangarajan, Sourav Saha | 2021-03-23 |
| 10657306 | Deep learning testability analysis with graph convolutional networks | Yuzhe Ma, Brucek Kurdo Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan | 2020-05-19 |
| 10545739 | LLVM-based system C compiler for architecture synthesis | Minsik Cho, Brian R. Konigsburg, Indira Nair, Jeonghee Shin | 2020-01-28 |
| 10502782 | Synthesis for random testability using unreachable states in integrated circuits | Victor N. Kravets, Mary P. Kusko, Spencer K. Millican | 2019-12-10 |
| 10223491 | Integrated circuit design changes using through-silicon vias | Harry Barowski, Joachim Keinert, Sridhar H. Rangarajan, Sourav Saha | 2019-03-05 |
| 9665674 | Automating a microarchitecture design exploration environment | Minsik Cho, Brian R. Konigsburg, Indira Nair, Jeonghee Shin | 2017-05-30 |
| 9633928 | Through-silicon via access device for integrated circuits | Harry Barowski, Joachim Keinert, Sridhar H. Rangarajan, Sourav Saha | 2017-04-25 |
| 9569580 | Integrated circuit design changes using through-silicon vias | Harry Barowski, Joachim Keinert, Sridhar H. Rangarajan, Sourav Saha | 2017-02-14 |
| 9563736 | Placement aware functional engineering change order extraction | George Antony, Pinaki Chakrabarti, Sourav Saha | 2017-02-07 |
| 9507891 | Automating a microarchitecture design exploration environment | Minsik Cho, Brian R. Konigsburg, Indira Nair, Jeonghee Shin | 2016-11-29 |
| 9501603 | Integrated circuit design changes using through-silicon vias | Harry Barowski, Joachim Keinert, Sridhar H. Rangarajan, Sourav Saha | 2016-11-22 |
| 9412682 | Through-silicon via access device for integrated circuits | Harry Barowski, Joachim Keinert, Sridhar H. Rangarajan, Sourav Saha | 2016-08-09 |
| 9405866 | Automating a microarchitecture design exploration environment | Minsik Cho, Brian R. Konigsburg, Indira Nair, Jeonghee Shin | 2016-08-02 |