Issued Patents All Time
Showing 126–150 of 496 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10566417 | Self-forming spacers using oxidation | Kevin K. Chan, Masaharu Kobayashi | 2020-02-18 |
| 10566247 | Local wiring in between stacked devices | — | 2020-02-18 |
| 10559493 | Multifunction single via patterning | — | 2020-02-11 |
| 10546926 | III-V semiconductor devices with selective oxidation | Cheng-Wei Cheng, Devendra K. Sadana | 2020-01-28 |
| 10546878 | Asymmetric junction engineering for narrow band gap MOSFET | — | 2020-01-28 |
| 10545131 | DNA sequencing using MOSFET transistors | — | 2020-01-28 |
| 10535662 | Semiconductor structures including an integrated FinFET with deep trench capacitor and methods of manufacture | Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Theodorus E. Standaert +1 more | 2020-01-14 |
| 10529739 | Asymmetric band gap junctions in narrow band gap MOSFET | — | 2020-01-07 |
| 10529624 | Simple contact over gate on active area | — | 2020-01-07 |
| 10522686 | Vertical thin film transistor | — | 2019-12-31 |
| 10483156 | Non-embedded silicon bridge chip for multi-chip module | — | 2019-11-19 |
| 10475701 | Mixed wire structure and method of making the same | — | 2019-11-12 |
| 10461194 | Threshold voltage control using channel digital etch | — | 2019-10-29 |
| 10454239 | Wafer scale monolithic integration of lasers, modulators, and other optical components using ALD optical coatings | Ning Li, Jean-Oliver Plouchart, Devendra K. Sadana | 2019-10-22 |
| 10452973 | Smart logic device | — | 2019-10-22 |
| 10446490 | Junctionless back end of the line via contact | — | 2019-10-15 |
| 10438913 | Monolithic decoupling capacitor between solder bumps | — | 2019-10-08 |
| 10418493 | Tight pitch stack nanowire isolation | — | 2019-09-17 |
| 10396147 | Grated MIM capacitor to improve capacitance | — | 2019-08-27 |
| 10389090 | Lateral growth of edge-emitting lasers | Ning Li, Tak H. Ning | 2019-08-20 |
| 10367060 | III-V semiconductor devices with selective oxidation | Cheng-Wei Cheng, Devendra K. Sadana | 2019-07-30 |
| 10361300 | Asymmetric vertical device | — | 2019-07-23 |
| 10361207 | Semiconductor structures with deep trench capacitor and methods of manufacture | Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Theodorus E. Standaert +1 more | 2019-07-23 |
| 10347717 | Fabrication of nanowire vertical gate devices | — | 2019-07-09 |
| 10347657 | Semiconductor circuit including nanosheets and fins on the same wafer | — | 2019-07-09 |