Issued Patents All Time
Showing 101–125 of 496 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10741611 | Resistive processing units with complementary metal-oxide-semiconductor non-volatile analog memory | — | 2020-08-11 |
| 10741560 | High resistance readout FET for cognitive device | — | 2020-08-11 |
| 10741532 | Multi-chip modules | — | 2020-08-11 |
| 10714419 | Non-planar metal-insulator-metal capacitor formation | — | 2020-07-14 |
| 10700017 | Interchip backside connection | — | 2020-06-30 |
| 10679904 | Stacked vertical devices | — | 2020-06-09 |
| 10672983 | Compact resistive random access memory integrated with a pass gate transistor | — | 2020-06-02 |
| 10658484 | Non-planar field effect transistor devices with wrap-around source/drain contacts | — | 2020-05-19 |
| 10658483 | Non-planar field effect transistor devices with wrap-around source/drain contacts | — | 2020-05-19 |
| 10629680 | Sidewall image transfer nanosheet | Tenko Yamashita | 2020-04-21 |
| 10629601 | Transistor and capacitor structures for analog memory neural network | — | 2020-04-21 |
| 10622283 | Self-contained liquid cooled semiconductor packaging | — | 2020-04-14 |
| 10622207 | Low external resistance channels in III-V semiconductor devices | Yanning Sun | 2020-04-14 |
| 10615178 | Dual-material mandrel for epitaxial crystal growth on silicon | Sanghoon Lee, Brent A. Wacaser | 2020-04-07 |
| 10607838 | Well and punch through stopper formation using conformal doping | Tenko Yamashita | 2020-03-31 |
| 10605985 | Integration of bonded optoelectronics, photonics waveguide and VLSI SOI | Russell A. Budd, Ning Li, Jean-Olivier Plouchart, Devendra K. Sadana | 2020-03-31 |
| 10601199 | Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same | Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu | 2020-03-24 |
| 10600912 | Self-aligned replacement metal gate spacerless vertical field effect transistor | — | 2020-03-24 |
| 10600891 | Smoothing surface roughness of III-V semiconductor fins formed from silicon mandrels by regrowth | Tze-Chiang Chen, Cheng-Wei Cheng, Sanghoon Lee | 2020-03-24 |
| 10600795 | Integration of floating gate memory and logic device in replacement gate flow | — | 2020-03-24 |
| 10600783 | Self-cut sidewall image transfer process | — | 2020-03-24 |
| 10593784 | Double patterning epitaxy Fin | — | 2020-03-17 |
| 10586853 | Non-planar field effect transistor devices with wrap-around source/drain contacts | — | 2020-03-10 |
| 10580900 | Nanosheet channel post replacement gate process | — | 2020-03-03 |
| 10573558 | Caterpillar trenches for efficient wafer dicing | Ghavam G. Shahidi | 2020-02-25 |