Issued Patents All Time
Showing 176–200 of 496 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10242991 | Highly compact floating gate analog memory | Yulong Li, Paul M. Solomon, Chun-Chen Yeh | 2019-03-26 |
| 10224415 | Integrated vertical nanowire memory | — | 2019-03-05 |
| 10218150 | Wafer scale monolithic integration of lasers, modulators, and other optical components using ALD optical coatings | Ning Li, Jean-Oliver Plouchart, Devendra K. Sadana | 2019-02-26 |
| 10217659 | Dual isolation fin and method of making | Cheng-Wei Cheng, Sanghoon Lee | 2019-02-26 |
| 10217512 | Unit cell with floating gate MOSFET for analog memory | — | 2019-02-26 |
| 10211225 | FinFET devices wit multiple channel lengths | Tenko Yamashita | 2019-02-19 |
| 10211109 | Local wiring in between stacked devices | — | 2019-02-19 |
| 10205003 | Surface roughness of III-V fin formed on silicon sidewall by implementing sacrificial buffers | Cheng-Wei Cheng, Sanghoon Lee, Renee T. Mo | 2019-02-12 |
| 10204907 | Metal-insulator-metal capacitor analog memory unit cell | Yulong Li, Paul M. Solomon, Chun-Chen Yeh | 2019-02-12 |
| 10192864 | Lateral BiCMOS replacement metal gate | Jin Cai, Tak H. Ning | 2019-01-29 |
| 10177254 | III-V compound semiconductor channel post replacement gate | — | 2019-01-08 |
| 10177047 | Trench gate first CMOS | — | 2019-01-08 |
| 10168473 | Integration of bonded optoelectronics, photonics waveguide and VLSI SOI | Russell A. Budd, Ning Li, Jean-Olivier Plouchart, Devendra K. Sadana | 2019-01-01 |
| 10170551 | Sidewall image transfer nanosheet | Tenko Yamashita | 2019-01-01 |
| 10170558 | Localized and self-aligned punch through stopper doping for finFET | Tenko Yamashita | 2019-01-01 |
| 10141048 | Stack capacitor for neural network | — | 2018-11-27 |
| 10141277 | Monolithic decoupling capacitor between solder bumps | — | 2018-11-27 |
| 10141719 | Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same | Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu | 2018-11-27 |
| 10134472 | Floating gate architecture for deep neural network application | Yulong Li, Paul M. Solomon, Chun-Chen Yeh | 2018-11-20 |
| 10135226 | Resonant cavity strained Group III-V photodetector and LED on silicon substrate and method to fabricate same | Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu | 2018-11-20 |
| 10128199 | Interchip backside connection | — | 2018-11-13 |
| 10122153 | Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same | Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu | 2018-11-06 |
| 10109575 | Non-planar metal-insulator-metal capacitor formation | — | 2018-10-23 |
| 10103242 | Growing groups III-V lateral nanowire channels | Sanghoon Lee, Renee T. Mo, Brent A. Wacaser | 2018-10-16 |
| 10103237 | Inverted MOSFET with scaling advantage | — | 2018-10-16 |