Issued Patents All Time
Showing 26–44 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9251111 | Command rate configuration in data processing system | Guy L. Guthrie, David J. Krolak, Praveen S. Reddy, Michael S. Siegel | 2016-02-02 |
| 9208091 | Coherent attached processor proxy having hybrid directory | Bartholomew Blaner, Michael S. Siegel, Jeffrey A. Stuecheli | 2015-12-08 |
| 9208092 | Coherent attached processor proxy having hybrid directory | Bartholomew Blaner, Michael S. Siegel, Jeffrey A. Stuecheli | 2015-12-08 |
| 9176877 | Provision of early data from a lower level cache memory | John T. Hollaway, Jr., Eric E. Retter, Jeffrey A. Stuecheli | 2015-11-03 |
| 9122608 | Frequency determination across an interface of a data processing system | John T. Hollaway, Jr., Praveen S. Reddy | 2015-09-01 |
| 9086975 | Coherent proxy for attached processor | Bartholomew Blaner, Michael S. Siegel, William J. Starke, Jeff A. Stuecheli | 2015-07-21 |
| 9069674 | Coherent proxy for attached processor | Bartholomew Blaner, Michael S. Siegel, William J. Starke, Jeff A. Stuecheli | 2015-06-30 |
| 9058273 | Frequency determination across an interface of a data processing system | John T. Hollaway, Jr., Praveen S. Reddy | 2015-06-16 |
| 8893126 | Binding a process to a special purpose processing element having characteristics of a processor | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Guy L. Guthrie, William J. Starke | 2014-11-18 |
| 8656128 | Aggregate data processing system having multiple overlapping synthetic computers | Guy L. Guthrie, William J. Starke, Derek E. Williams | 2014-02-18 |
| 8429382 | Information handling system including a multiple compute element processor with distributed data on-ramp data-off ramp topology | Robert Alan Cargnoni, Gary Alan Gorman, Julie Ann Rosser | 2013-04-23 |
| 8370595 | Aggregate data processing system having multiple overlapping synthetic computers | Guy L. Guthrie, William J. Starke, Derek E. Williams | 2013-02-05 |
| 7917730 | Processor chip with multiple computing elements and external i/o interfaces connected to perpendicular interconnection trunks communicating coherency signals via intersection bus controller | John T. Holloway, Praveen S. Reddy, William J. Starke | 2011-03-29 |
| 7865650 | Processor with coherent bus controller at perpendicularly intersecting axial bus layout for communication among SMP compute elements and off-chip I/O elements | John T. Holloway, Praveen S. Reddy, William J. Starke | 2011-01-04 |
| 6999105 | Image scaling employing horizontal partitioning | Daniel J. Buerkle, David A. Hrusecky, Chuck H. Ngai, John William Urda | 2006-02-14 |
| 6803922 | Pixel formatter for two-dimensional graphics engine of set-top box system | — | 2004-10-12 |
| 6784893 | Raster operation unit | — | 2004-08-31 |
| 6061403 | Computer program product for selectively reducing bandwidth of real-time video data | — | 2000-05-09 |
| 5986714 | Method, apparatus and computer program product for selectively reducing bandwidth of real-time video data | — | 1999-11-16 |