BV

Brian T. Vanderpool

IBM: 40 patents #2,346 of 70,183Top 4%
3M: 1 patents #7,233 of 11,543Top 65%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
📍 Byron, MN: #7 of 105 inventorsTop 7%
🗺 Minnesota: #1,180 of 52,454 inventorsTop 3%
Overall (All Time): #71,287 of 4,157,543Top 2%
42
Patents All Time

Issued Patents All Time

Showing 26–42 of 42 patents

Patent #TitleCo-InventorsDate
8879553 Multicast bandwidth multiplication for a unified distributed switch Claude Basso, Todd A. Greenfield, Philip Hillier, Mark L. Rudquist, Kenneth M. Walk +1 more 2014-11-04
8812793 Silent invalid state transition handling in an SMP environment Marcus L. Kornegay, Ngan N. Pham 2014-08-19
8195892 Structure for silent invalid state transition handling in an SMP environment Marcus L. Kornegay, Ngan N. Pham 2012-06-05
8082396 Selecting a command to send to memory Herman L. Blackmon, Philip Hillier, Joseph A. Kirscht 2011-12-20
8010682 Early coherency indication for return data in shared memory architecture Wayne M. Barrett, David A. Shedivy, Kenneth M. Valk 2011-08-30
7890708 Prioritization of out-of-order data transfers on shared data bus Wayne M. Barrett 2011-02-15
7761669 Memory controller granular read queue dynamic optimization of command selection Brian Allison, Wayne M. Barrett, Joseph A. Kirscht, Elizabeth A. McGlone 2010-07-20
7650259 Method for tuning chipset parameters to achieve optimal performance under varying workload types Herman L. Blackmon, Joseph A. Kirscht, David A. Shedivy 2010-01-19
7577793 Patrol snooping for higher level cache eviction candidate identification John Michael Borkenhagen 2009-08-18
7536514 Early return indication for read exclusive requests in shared memory architecture Wayne M. Barrett, Kenneth M. Valk 2009-05-19
7519510 Derivative performance counter mechanism Brian Lee Koehler 2009-04-14
7392353 Prioritization of out-of-order data transfers on shared data bus Wayne M. Barrett 2008-06-24
7010654 Methods and systems for re-ordering commands to access memory Herman L. Blackmon, Joseph A. Kirscht, James Anthony Marcella 2006-03-07
6836831 Independent sequencers in a DRAM control structure John Michael Borkenhagen, Robert Allen Drehmel 2004-12-28
6801982 Read prediction algorithm to provide low latency reads with SDRAM cache John Michael Borkenhagen, Lawrence D. Whitley 2004-10-05
6754858 SDRAM address error detection method and apparatus John Michael Borkenhagen 2004-06-22
5781773 Method for transforming and storing data for search and display and a searching system utilized therewith Thomas R. Vanderpool, Craig K. Lenz, TJ Parro, John Threlfall 1998-07-14