| 8996812 |
Write-back coherency data cache for resolving read/write conflicts |
Marcus L. Kornegay |
2015-03-31 |
| 8838909 |
Dynamic initial cache line coherency state assignment in multi-processor systems |
Daniel J. Colglazier, Marcus L. Kornegay, Cristian G. Rojas |
2014-09-16 |
| 8812793 |
Silent invalid state transition handling in an SMP environment |
Marcus L. Kornegay, Brian T. Vanderpool |
2014-08-19 |
| 8195892 |
Structure for silent invalid state transition handling in an SMP environment |
Marcus L. Kornegay, Brian T. Vanderpool |
2012-06-05 |
| 8131943 |
Structure for dynamic initial cache line coherency state assignment in multi-processor systems |
Daniel J. Colglazier, Marcus L. Kornegay, Cristian G. Rojas |
2012-03-06 |
| 8065487 |
Structure for shared cache eviction |
Marcus L. Kornegay |
2011-11-22 |
| 7925838 |
Directory-based data transfer protocol for multiprocessor system |
Chris Dombrowski, Marcus L. Kornegay |
2011-04-12 |
| 7865669 |
System and method for dynamically selecting the fetch path of data for improving processor performance |
Marcus L. Kornegay |
2011-01-04 |
| 7844779 |
Method and system for intelligent and dynamic cache replacement management based on efficient use of cache for individual processor core |
Marcus L. Kornegay |
2010-11-30 |
| 7840759 |
Shared cache eviction |
Marcus L. Kornegay |
2010-11-23 |
| 7457920 |
Method and system for cache eviction |
Marcus L. Kornegay |
2008-11-25 |
| 7404045 |
Directory-based data transfer protocol for multiprocessor system |
Chris Dombrowski, Marcus L. Kornegay |
2008-07-22 |
