Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11030115 | Dataless cache entry | — | 2021-06-08 |
| 10853267 | Adaptive method for selecting a cache line replacement algorithm in a direct-mapped cache | — | 2020-12-01 |
| 10387330 | Less recently and frequently used (LRAFU) cache replacement policy | — | 2019-08-20 |
| 10176118 | Alternative direct-mapped cache and cache replacement method | — | 2019-01-08 |
| 8838909 | Dynamic initial cache line coherency state assignment in multi-processor systems | Marcus L. Kornegay, Ngan N. Pham, Cristian G. Rojas | 2014-09-16 |
| 8745334 | Sectored cache replacement algorithm for reducing memory writebacks | — | 2014-06-03 |
| 8131943 | Structure for dynamic initial cache line coherency state assignment in multi-processor systems | Marcus L. Kornegay, Ngan N. Pham, Cristian G. Rojas | 2012-03-06 |
| 6715035 | Cache for processing data in a memory controller and a method of use thereof to reduce first transfer latency | Chris Dombrowski, Thomas B. Genduso | 2004-03-30 |
| 5999721 | Method and system for the determination of performance characteristics of a cache design by simulating cache operations utilizing a cache output trace | — | 1999-12-07 |