Issued Patents All Time
Showing 26–40 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6973520 | System and method for providing improved bus utilization via target directed completion | Bernard C. Drerup, Jaya Prakash Subramaniam Ganasan, Richard Gerard Hofmann, Richard Nicholas Iachetta, Jr. | 2005-12-06 |
| 6970962 | Transfer request pipeline throttling | James Norris Dieffenderfer, Bernard C. Drerup, Jaya Prakash Subramaniam Ganasan, Richard Gerard Hofmann, Thomas Andrew Sartorius +1 more | 2005-11-29 |
| 6907502 | Method for moving snoop pushes to the front of a request queue | Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard C. Drerup, Jaya Prakash Subramaniam Ganasan, Richard Gerard Hofmann +2 more | 2005-06-14 |
| 6834378 | System on a chip bus with automatic pipeline stage insertion for timing closure | Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard C. Drerup, Richard Gerard Hofmann, Thomas Andrew Sartorius | 2004-12-21 |
| 6826656 | Reducing power in a snooping cache based multiprocessor environment | Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard C. Drerup, Richard Gerard Hofmann, Thomas Andrew Sartorius | 2004-11-30 |
| 6823411 | N-way psuedo cross-bar having an arbitration feature using discrete processor local busses | Richard Gerard Hofmann | 2004-11-23 |
| 6807608 | Multiprocessor environment supporting variable-sized coherency transactions | Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard C. Drerup, Richard Gerard Hofmann, Thomas Andrew Sartorius | 2004-10-19 |
| 6504790 | Configurable DDR write-channel phase advance and delay capability | — | 2003-01-07 |
| 6493285 | Method and apparatus for sampling double data rate memory read data | — | 2002-12-10 |
| 6452865 | Method and apparatus for supporting N-bit width DDR memory interface using a common symmetrical read data path with 2N-bit internal bus width | — | 2002-09-17 |
| 6424198 | Memory clock generation with configurable phase advance and delay capability | — | 2002-07-23 |
| 6266741 | Method and apparatus to reduce system bus latency on a cache miss with address acknowledgments | Chau-Shing Hui, Krishnamurthy Venkatramani | 2001-07-24 |
| 6134620 | Tri-state bus contention circuit preventing false switching caused by poor synchronization | Chau-Shing Hui, Krishnamurthy Venkatramani | 2000-10-17 |
| 5664165 | Generation of a synthetic clock signal in synchronism with a high frequency clock signal and corresponding to a low frequency clock signal | Sean Eugene Curry | 1997-09-02 |
| 5535226 | On-chip ECC status | Charles E. Drake, John A. Fifield, Richard D. Wheeler | 1996-07-09 |