Issued Patents All Time
Showing 176–184 of 184 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6249029 | Device method for enhanced avalanche SOI CMOS | William F. Clark, Jr., John J. Ellis-Monaghan, Edward P. Maciejewski, Edward J. Nowak, Wilbur D. Pricer +1 more | 2001-06-19 |
| 6239591 | Method and apparatus for monitoring SOI hysterises effects | Edward J. Nowak, Minh H. Tong | 2001-05-29 |
| 6200843 | High-voltage, high performance FETs | Edward J. Nowak, Minh H. Tong | 2001-03-13 |
| 6159807 | Self-aligned dynamic threshold CMOS device | Edward J. Nowak | 2000-12-12 |
| 6100564 | SOI pass-gate disturb solution | Edward J. Nowak, Minh H. Tong | 2000-08-08 |
| 5959335 | Device design for enhanced avalanche SOI CMOS | William F. Clark, Jr., John J. Ellis-Monaghan, Edward P. Maciejewski, Edward J. Nowak, Wilbur D. Pricer +1 more | 1999-09-28 |
| 5793082 | Self-aligned gate sidewall spacer in a corrugated FET | — | 1998-08-11 |
| 5512517 | Self-aligned gate sidewall spacer in a corrugated FET and method of making same | — | 1996-04-30 |
| 5049461 | Method of making and using a high resolution lithographic mask | Patrick Clinton Arnett, John S. Foster, Jane Elizabeth Frommer, Jon A. C. Iwata | 1991-09-17 |