Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5856926 | Logic synthesis method and system with intermediate circuit files | Kazuhiko Matsumoto, Takao Shinsha, Nobuyuki Hayashi, Hiromoto Sakaki, Miyako Tandai +3 more | 1999-01-05 |
| 5809039 | Semiconductor integrated circuit device with diagnosis function | Toshiro Takahashi, Fumihiko Shirotori, Masahiko Nagai | 1998-09-15 |
| 5184308 | Fault simulation method | Masahiko Nagai, Hiroo Watai, Takaharu Nagumo | 1993-02-02 |
| 4891773 | Logic simulation | Kimio Ooe, Nobutaka Amano, Takashige Kubo | 1990-01-02 |
| 4703257 | Logic circuit having a test data scan circuit | Takao Nishida, Toru Hiyama, Shun Ishiyama, Shunsuke Miyamoto | 1987-10-27 |