Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5745373 | Logic circuit generating method and apparatus | Akira Yamaoka, Kazuhiko Matsumoto, Hiromoto Sakaki | 1998-04-28 |
| 5467292 | Logical operation method employing parallel arithmetic unit | Takao Nishida, Takaharu Nagumo, Masahiko Nagai | 1995-11-14 |
| 5184308 | Fault simulation method | Masahiko Nagai, Takaharu Nagumo, Kaoru Moriwaki | 1993-02-02 |