Issued Patents All Time
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5856926 | Logic synthesis method and system with intermediate circuit files | Kazuhiko Matsumoto, Takao Shinsha, Nobuyuki Hayashi, Hiromoto Sakaki, Yasunori Yamada +3 more | 1999-01-05 |