Issued Patents All Time
Showing 51–64 of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6023751 | Computer system and method for evaluating predicates and Boolean expressions | B. Ramakrishna Rau, Vinod K. Kathail | 2000-02-08 |
| 5999738 | Flexible scheduling of non-speculative instructions | Vinod K. Kathail | 1999-12-07 |
| 5920716 | Compiling a predicated code with direct analysis of the predicated code | Richard Craig Johnson | 1999-07-06 |
| 5850553 | Reducing the number of executed branch instructions in a code sequence | Vinod K. Kathail | 1998-12-15 |
| 5778219 | Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations | Frederic C. Amerson, Rajiv Gupta, Vinod K. Kathail, B. Ramakrishna Rau, William S. Worley, Jr. | 1998-07-07 |
| 5742804 | Instruction prefetch mechanism utilizing a branch predict instruction | Tse-Yu Yeh, Mircea Poplingher, Kent Fielden, Hans Mulder, Rajiv Gupta +1 more | 1998-04-21 |
| 5710912 | Method and apparatus for enabling a computer system to adjust for latency assumptions | B. Ramakrishna Rau, Rajiv Gupta, Joseph Fisher | 1998-01-20 |
| 5692169 | Method and system for deferring exceptions generated during speculative execution | Vinod K. Kathail, Rajiv Gupta, Bantwal R. Rau, William S. Worley, Jr., Frederic C. Amerson | 1997-11-25 |
| 5664135 | Apparatus and method for reducing delays due to branches | Vinod K. Kathail | 1997-09-02 |
| 5615386 | Computer architecture for reducing delays due to branch instructions | Frederic C. Amerson, Rajiv Gupta, Balasubramanian Kumar, William S. Worley, Jr. | 1997-03-25 |
| 5475823 | Memory processor that prevents errors when load instructions are moved in the execution sequence | Frederic C. Amerson, Rajiv Gupta, Vinod K. Kathail | 1995-12-12 |
| 5404484 | Cache system for reducing memory latency times | Vinod K. Kathail, Rajiv Gupta | 1995-04-04 |
| 5293631 | Analysis and optimization of array variables in compiler for instruction level parallel processor | Bantwai R. Rau | 1994-03-08 |
| 5276826 | Apparatus for transforming addresses to provide pseudo-random access to memory modules | Bantwal R. Rau | 1994-01-04 |