Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8023307 | Peripheral signal handling in extensible three dimensional circuits | Richard J. Carter | 2011-09-20 |
| 7084910 | System and method for using multiple images in a digital image capture device | Paul M. Hubel, Donald J. Stavely, Charles H. McConica, K Douglas Gennetten, Susan Hunter +1 more | 2006-08-01 |
| 6379022 | Auxiliary illuminating device having adjustable color temperature | Paul M. Hubel, Ricardo J. Motta | 2002-04-30 |
| 5945841 | Block segmentation of configuration lines for fault tolerant programmable logic device | William R. Mason | 1999-08-31 |
| 5946190 | Ducted high aspect ratio heatsink assembly | Chandrakant Patel, Christian L. Belady | 1999-08-31 |
| 5778219 | Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations | Rajiv Gupta, Vinod K. Kathail, B. Ramakrishna Rau, Michael Schlansker, William S. Worley, Jr. | 1998-07-07 |
| 5721865 | Information processing apparatus with prefetch control for prefetching data structure from memory through cache memory | Yooichi Shintani, Yoshikazu Tanaka, Naohiko Irie, William S. Worley, Jr., B. Ramakrishna Rau +1 more | 1998-02-24 |
| 5721498 | Block segmentation of configuration lines for fault tolerant programmable logic device | William R. Mason | 1998-02-24 |
| 5692169 | Method and system for deferring exceptions generated during speculative execution | Vinod K. Kathail, Rajiv Gupta, Bantwal R. Rau, Michael Schlansker, William S. Worley, Jr. | 1997-11-25 |
| 5689653 | Vector memory operations | Alan H. Karp, Dennis W. Brzezinski, Rajiv Gupta, William S. Worley, Jr. | 1997-11-18 |
| 5615386 | Computer architecture for reducing delays due to branch instructions | Rajiv Gupta, Balasubramanian Kumar, Michael Schlansker, William S. Worley, Jr. | 1997-03-25 |
| 5564031 | Dynamic allocation of registers to procedures in a digital computer | Robert M. English, Rajiv Gupta, Tan Watanabe | 1996-10-08 |
| 5475823 | Memory processor that prevents errors when load instructions are moved in the execution sequence | Rajiv Gupta, Vinod K. Kathail, Michael Schlansker | 1995-12-12 |