Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12324213 | Stress layout optimization for device performance | Dirk Utess, Dominik Martin Kleimaier, Irfan Saadat, Florent Ravaux | 2025-06-03 |
| 12308801 | Back-gate controlled power amplifier | Yiching Chen | 2025-05-20 |
| 12268019 | Ferroelectric field-effect transistors with a hybrid well | Stefan Dünkel, Dominik Martin Kleimaier, Halid Mulaosmanovic | 2025-04-01 |
| 12046670 | Semiconductor device having a gate contact over an active region | Manjunatha Prabhu, Shafiullah Syed | 2024-07-23 |
| 11916109 | Bipolar transistor structures with base having varying horizontal width and methods to form same | Peter Baars, Alexander M. Derrickson, Ketankumar Harishbhai Tailor, Judson R. Holt | 2024-02-27 |
| 11837605 | Structure including transistor using buried insulator layer as gate dielectric and trench isolations in source and drain | Tom Herrmann, Alban Zaka, Yiching Chen | 2023-12-05 |
| 11664432 | Stress layout optimization for device performance | Dirk Utess, Dominik Martin Kleimaier, Irfan Saadat, Florent Ravaux | 2023-05-30 |