Issued Patents All Time
Showing 51–75 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9035629 | Voltage regulator with different inverting gain stages | — | 2015-05-19 |
| 9021194 | Memory management unit tag memory | David R. Bearden, Prashant U. Kenkare, Jogendra C. Sarker | 2015-04-28 |
| 8943292 | System and method for memory array access with fast address decoder | David R. Bearden, Prashant U. Kenkare | 2015-01-27 |
| 8941427 | Configurable flip-flop | Shayan Zhang | 2015-01-27 |
| 8917136 | Charge pump system and method of operation | Perry H. Pelley, Michael G. Neaves | 2014-12-23 |
| 8914712 | Hierarchical error correction | Ajay Joshi, Bobak A. Nazer | 2014-12-16 |
| 8908449 | Master-slave flip-flop with reduced setup time | — | 2014-12-09 |
| 8861301 | Clocked memory with latching predecoder circuitry | Hema Ramamurthy | 2014-10-14 |
| 8837205 | Multi-port register file with multiplexed data | Perry H. Pelley, Andrew C. Russell | 2014-09-16 |
| 8806294 | Error detection within a memory | — | 2014-08-12 |
| 8791739 | Flip-flop having shared feedback and method of operation | Prashant U. Kenkare | 2014-07-29 |
| 8755244 | Write contention-free, noise-tolerant multi-port bitcell | Ambica Ashok, Andrew C. Russell | 2014-06-17 |
| 8743651 | Clocked memory with word line activation during a first portion of the clock cycle | Hema Ramamurthy | 2014-06-03 |
| 8710916 | Electronic circuit having shared leakage current reduction circuits | David R. Bearden, Andrew C. Russell, Shayan Zhang | 2014-04-29 |
| 8677205 | Hierarchical error correction for large memories | Edmund J. Gieske, David F. Greenberg | 2014-03-18 |
| 8587356 | Recoverable and reconfigurable pipeline structure for state-retention power gating | Shayan Zhang, William C. Moyer | 2013-11-19 |
| 8566620 | Data processing having multiple low power modes and method therefor | Andrew C. Russell, Shayan Zhang | 2013-10-22 |
| 8566836 | Multi-core system on chip | David R. Bearden, William C. Moyer | 2013-10-22 |
| 8542048 | Double edge triggered flip flop | — | 2013-09-24 |
| 8537625 | Memory voltage regulator with leakage current voltage control | Shayan Zhang, Kenneth R. Burch, Charles E. Seaberg, Andrew C. Russell | 2013-09-17 |
| 8533578 | Error detection in a content addressable memory (CAM) and method of operation | Ambica Ashok, Kent Li | 2013-09-10 |
| 8514611 | Memory with low voltage mode operation | Huy B. Nguyen, Troy L. Cooper, Andrew C. Russell | 2013-08-20 |
| 8493121 | Reconfigurable flip-flop | — | 2013-07-23 |
| 8489906 | Data processor having multiple low power modes | David R. Bearden, Troy L. Cooper | 2013-07-16 |
| 8487657 | Dynamic logic circuit | George P. Hoekstra, Maciej Bajkowski | 2013-07-16 |