Issued Patents All Time
Showing 25 most recent of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11581056 | Apparatuses and methods for direct access hybrid testing | Chikara Kondo, Roman A. Royer | 2023-02-14 |
| 11156658 | Semiconductor memory device | — | 2021-10-26 |
| 11120849 | Semiconductor layered device with data bus | Chikara Kondo | 2021-09-14 |
| 11067628 | Replication of a first interface onto a second interface and related systems, methods, and devices | Chikara Kondo, Ryo Fujimaki | 2021-07-20 |
| 10943625 | Memory device with write data bus control | Chikara Kondo, Tomoyuki Shibata, Seiji Narui, Minehiko Uehara, Taihei Shido +1 more | 2021-03-09 |
| 10937518 | Multiple algorithmic pattern generator testing of a memory device | Roman A. Royer, Chikara Kondo | 2021-03-02 |
| 10896738 | Apparatuses and methods for direct access hybrid testing | Chikara Kondo, Roman A. Royer | 2021-01-19 |
| 10854310 | Shared error detection and correction memory | Taihei Shido, Yuki Ebihara | 2020-12-01 |
| 10839889 | Apparatuses and methods for providing clocks to data paths | Hyunui Lee, Chikara Kondo | 2020-11-17 |
| 10790039 | Semiconductor device having a test circuit | Hyunui Lee | 2020-09-29 |
| 10636461 | Apparatuses and methods for providing multiphase clock signals | Homare Sato, Chikara Kondo | 2020-04-28 |
| 10553263 | Memory device with write data bus control | Chikara Kondo, Tomoyuki Shibata, Seiji Narui, Minehiko Uehara, Taihei Shido +1 more | 2020-02-04 |
| 10468114 | Shared error detection and correction memory | Taihei Shido, Yuki Ebihara | 2019-11-05 |
| 10373657 | Semiconductor layered device with data bus | Chikara Kondo | 2019-08-06 |
| 10365325 | Semiconductor memory device | — | 2019-07-30 |
| 10338997 | Apparatuses and methods for fixing a logic level of an internal signal line | Seiichi Maruno, Taihei Shido, Toshio Ninomiya, Chikara Kondo | 2019-07-02 |
| 10262704 | Apparatuses and methods for providing multiphase clock signals | Homare Sato, Chikara Kondo | 2019-04-16 |
| 10163469 | System and method for write data bus control in a stacked memory device | Chikara Kondo, Tomoyuki Shibata, Seiji Narui, Minehiko Uehara, Taihei Shido +1 more | 2018-12-25 |
| 10008287 | Shared error detection and correction memory | Taihei Shido, Yuki Ebihara | 2018-06-26 |
| 9983925 | Apparatuses and methods for fixing a logic level of an internal signal line | Seiichi Maruno, Taihei Shido, Toshio Ninomiya, Chikara Kondo | 2018-05-29 |
| 9412432 | Semiconductor storage device and system provided with same | Seiji Narui, Hiromasa Noda, Chikara Kondo, Masayuki Nakamura | 2016-08-09 |
| 9130556 | Semiconductor device having output buffer circuit in which impedance thereof can be controlled | Takenori Sato, Shinya Miyazaki | 2015-09-08 |
| 9030888 | Semiconductor device having output buffer circuit in which impedance thereof can be controlled | Shinya Miyazaki | 2015-05-12 |
| 9030233 | Semiconductor device having serializer converting parallel data into serial data to output serial data from output buffer circuit | Shinya Miyazaki | 2015-05-12 |
| 8947128 | Semiconductor device having input receiver circuit that operates in response to strobe signal | Seiji Narui, Seiichi Maruno | 2015-02-03 |