Issued Patents All Time
Showing 51–75 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9306025 | Memory transistor with multiple charge storing layers and a high work function gate electrode | Sagy Levy, Krishnaswamy Ramkumar | 2016-04-05 |
| 9201106 | Self shielding capacitance sensing panel | Min Chin Chai, Fred Keiser | 2015-12-01 |
| 9128577 | Hybrid capacitive touch system design and method | — | 2015-09-08 |
| 9116558 | Executing gestures with active stylus | Esat Yilmaz, Trond Jarle Pedersen, John Logan, Vemund Kval Bakken, Kishore Sundara-Rajan +1 more | 2015-08-25 |
| 9105740 | SONOS type stacks for nonvolatile changetrap memory devices and methods to form the same | Helmut Puchner, Sagy Levy | 2015-08-11 |
| 9093318 | Memory transistor with multiple charge storing layers and a high work function gate electrode | Sagy Levy, Krishnaswamy Ramkumar | 2015-07-28 |
| 8860122 | Nonvolatile charge trap memory device having a high dielectric constant blocking region | Sagy Levy | 2014-10-14 |
| 8859374 | Memory transistor with multiple charge storing layers and a high work function gate electrode | Sagy Levy, Krishnaswamy Ramkumar | 2014-10-14 |
| 8780073 | Capacitive sensor arrangement | Vasyl Mandziy | 2014-07-15 |
| 8691648 | Methods for fabricating semiconductor memory with process induced strain | Sagy Levy, Krishnaswamy Ramkumar, Jeong Soo Byun | 2014-04-08 |
| 8638310 | Capacitive touch screen | Edward L. Grivna | 2014-01-28 |
| 8633537 | Memory transistor with multiple charge storing layers and a high work function gate electrode | Sagy Levy, Krishnaswamy Ramkumar | 2014-01-21 |
| 8592891 | Methods for fabricating semiconductor memory with process induced strain | Sagy Levy, Krishnaswamy Ramkumar, Jeong Soo Byun | 2013-11-26 |
| 8482546 | Self shielding capacitance sensing panel | Min Chin Chai, Fred Keiser | 2013-07-09 |
| 8462135 | Multi-touch disambiguation | Browley Xiao, Nelson Chow, Victor P. Drake | 2013-06-11 |
| 8174510 | Capacitive touch screen | Edward L. Grivna | 2012-05-08 |
| 8163660 | SONOS type stacks for nonvolatile change trap memory devices and methods to form the same | Helmut Puchner, Sagy Levy | 2012-04-24 |
| 8063434 | Memory transistor with multiple charge storing layers and a high work function gate electrode | Sagy Levy, Krishnaswamy Ramkumar | 2011-11-22 |
| 7880219 | Nonvolatile charge trap memory device having <100> crystal plane channel orientation | Sagy Levy, Krishnaswamy Ramkumar | 2011-02-01 |
| 7678640 | Method of threshold voltage control in metal-oxide-semiconductor devices | Oliver Pohland | 2010-03-16 |
| 7629653 | Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors | Sharmin Sadoughi, Krishnaswamy Ramkumar, Ravindra M. Kapre, Maroun Georges Khoury | 2009-12-08 |
| 7384833 | Stress liner for integrated circuits | Krishnaswamy Ramkumar, Sagy Levy | 2008-06-10 |
| 7256087 | Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors | Sharmin Sadoughi, Krishnaswamy Ramkumar, Ravindra M. Kapre, Maroun Georges Khoury | 2007-08-14 |
| 7141858 | Dual work function CMOS gate technology based on metal interdiffusion | Pushkar Ranade, Tsu-Jae King, Chenming Hu | 2006-11-28 |
| 6794234 | Dual work function CMOS gate technology based on metal interdiffusion | Pushkar Ranade, Tsu-Jae King, Chenming Hu | 2004-09-21 |