Issued Patents All Time
Showing 26–50 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9280464 | System and method for simultaneously storing and reading data from a memory system | Shang-Tse Chuang | 2016-03-08 |
| 9274586 | Intelligent memory interface | Nick McKeown, Morgan Littlewood | 2016-03-01 |
| 9165687 | Methods and apparatus for testing and repairing digital memory circuits | Shadab Nazar, Sanjeev Joshi | 2015-10-20 |
| 9147466 | Methods and apparatus for designing and constructing dual write memory circuits with voltage assist | Shang-Tse Chuang, Thu Nguyen | 2015-09-29 |
| 9063876 | System and method for simultaneously storing and read data from a memory system | Shang-Tse Chuang | 2015-06-23 |
| 9058860 | Methods and apparatus for synthesizing multi-port memory circuits | Shang-Tse Chuang, Thu Nguyen, Sanjeev Joshi, Adam Kablanian | 2015-06-16 |
| 8935507 | System and method for storing multiple copies of data in a high speed memory system | Shang-Tse Chuang | 2015-01-13 |
| 8902672 | Methods and apparatus for designing and constructing multi-port memory circuits | Shang-Tse Chuang, Thu Nguyen, Sanjeev Joshi, Adam Kablanian, Kartik Mohanram | 2014-12-02 |
| RE45097 | High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory | Nick McKeown | 2014-08-26 |
| 8760958 | Methods and apparatus for designing and constructing multi-port memory circuits with voltage assist | Shang-Tse Chuang, Thu Nguyen | 2014-06-24 |
| 8677072 | System and method for reduced latency caching | Shang-Tse Chuang | 2014-03-18 |
| 8589851 | Intelligent memory system compiler | Sanjeev Joshi, Shang-Tse Chuang | 2013-11-19 |
| 8504796 | System and method for storing data in a virtualized high speed memory system with an integrated memory mapping table | Shang-Tse Chuang | 2013-08-06 |
| 8433880 | System and method for storing data in a virtualized high speed memory system | Shang-Tse Chuang | 2013-04-30 |
| 8266408 | System and method for storing data in a virtualized high speed memory system | Shang-Tse Chuang | 2012-09-11 |
| 7657706 | High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory | Nick McKeown | 2010-02-02 |
| 7362703 | Method for deflection routing of data packets to alleviate link overload in IP networks | Nina Taft, Supratik Bhattacharyya, Christophe Diot | 2008-04-22 |
| 7136926 | Method and apparatus for high-speed network rule processing | Raghunath Iyer, Moti Jiandani, Ramana Rao | 2006-11-14 |
| 7043494 | Fast, deterministic exact match look-ups in large tables | Deepali Joshi, Ajit Shelat, Amit Phansalkar, Ramana Rao Kompella, George Varghese | 2006-05-09 |
| 6972614 | Circuits associated with fusible elements for establishing and detecting of the states of those elements | Mark E. Anderson, Chandrasekara Kothandaraman, Edward P. Maciejewski, George E. Smith, III | 2005-12-06 |
| 6691168 | Method and apparatus for high-speed network rule processing | Subhash Bal, Raghunath Iyer, Ramana Rao | 2004-02-10 |
| 6631466 | Parallel string pattern searches in respective ones of array of nanocomputers | Vikram Chopra, Ajay Desai, Raghunath Iyer, Moti Jiandani, Ajit Shelat +1 more | 2003-10-07 |
| 6611875 | Control system for high speed rule processors | Vikram Chopra, Ajay Desai, Raghunath Iyer, Moti Jiandani, Ajit Shelat +1 more | 2003-08-26 |
| 6510509 | Method and apparatus for high-speed network rule processing | Vikram Chopra, Ajay Desai, Raghunath Iyer, Moti Jiandani, Ajit Shelat +1 more | 2003-01-21 |
| 6457061 | Method and apparatus for performing internet network address translation | Subhash Bal, Raghunath Iyer | 2002-09-24 |