Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10607039 | Constrained metric optimization of a system on chip | Yael Kinderman, Ido Avraham, Michele Petracca, Yosinori Watanabe | 2020-03-31 |
| 10423741 | Constrained metric verification analysis of a system on chip | Michele Petracca, Yosinori Watanabe, Yael Kinderman, Ido Avraham | 2019-09-24 |
| 8296697 | Method and apparatus for performing static analysis optimization in a design verification system | Amit Gal, Amos Noy | 2012-10-23 |
| 7870523 | System and method for test generation with dynamic constraints using static analysis and multidomain constraint reduction | Amos Noy, Vitaly Lagoon, Yael Kinderman, Amit Gal | 2011-01-11 |